СВЕРХПРОВОДНИК ТЕПЛОТЫ

Сверхтеплопроводящий материал состоит из трех основных слоев, первый слой состоит из различных комбинаций металлов и радикала дихромата; второй слой формируется поверх первого слоя и состоит из различных комбинаций металлов, таких как кобальт, марганец, бериллий, стронций и радикал дихромата; третий слой формируется поверх второго слоя и состоит из различных комбинаций оксидов металлов, дихроматов, монокристаллического кремния, хромата стронция и β-титана. Эти три слоя могут быть наложены на трубопроводе и подвергнуты тепловой поляризации с тем, чтобы сформировать сверхпроводящее теплоту устройство, передающее теплоту без потери теплоты в цепи, или могут быть наложены на пару пластин, имеющих полость малого объема по сравнению с площадью поверхности с тем, чтобы сформировать теплоотвод, который в состоянии очень быстро рассеивать теплоту от источника теплоты. Изобретение позволит получить недорогой в изготовлении, простой по дизайну, исполнению и использованию материал и устройство из него ...

ПРОИЗВОДСТВО ЧАСТИЦ И ИЗДЕЛИЙ С ЗАПРОЕКТИРОВАННЫМИ СВОЙСТВАМИ

Изобретение относится к производству изделий и покрытий, проектируемых так, чтобы иметь заранее выбранные удельные теплопроводности и коэффициенты температурного расширения (КТР), согласующиеся с такими же характеристиками тех материалов, к которым эти изделия и покры- тия прикрепляются. Изобретение включает способ придания частицам желательного значения удельной теплопроводности и/или КТР путем нанесения на них покрытия, сами покрытые частицы и изделия, изготовленные из множества покрытых частиц путем их объединения уплотнением, изостатическим прессованием или инжекционным формованием. Способ заключается в том, что на каждую частицу покрытие наносят в определенном объеме по отношению к объему самой частицы так, чтобы полученные значения удельной теплопроводности и/или КТР покрытой частицы отличались от значений этих свойств у материалов частиц и покрытия. В качестве материала частицы используют графит, алмаз, вольфрам или никель-42, а в качестве материала покрытия - медь. При определенных ...

СХЕМНЫЙ МОДУЛЬ И УСТРОЙСТВО СВЯЗИ ПО ЛИНИИ ЭЛЕКТРОПЕРЕДАЧИ

Использование: в области электронной техники. Технический результат заключается в повышении надежности и защиты от шума. Схемный модуль монтируется с ИС, которая модулирует и демодулирует сигнал с несколькими несущими. Схемный модуль имеет многослойную плату, которая изнутри снабжается множеством проводящих слоев, уложенных с изолирующими слоями между ними, и ИС, которая снабжается множеством выводов заземления, которые нужно заземлить. Из множества проводящих слоев проводящий слой, представленный ближайшим к ИС, формирует слой заземления, электрически соединенный с множеством выводов заземления. 2 н. и 14 з.п. ф-лы, 39 ил.

ЭЛЕКТРОННЫЙ МОДУЛЬ И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

... 1. Электронный модуль с имеющей по меньшей мере один электронный компонент первой подложкой и с изготовленным литьем под давлением или литьевым прессованием корпусом, в который заделана первая подложка, а также с выступающими из корпуса, соединенными с первой подложкой электрическими контактными выводами, выполненными в виде штампованной контактной решетки, отличающийся тем, что в корпус (25) заделана по меньшей мере еще одна - вторая - подложка (13) со вторыми электрическими контактными выводами (15), которые выполнены в виде второй штампованной контактной решетки (14), при этом обе штампованные контактные решетки (3, 14) непосредственно соединены между собой в по меньшей мере одном месте (19). ! 2. Электронный модуль по п.1, отличающийся тем, что по меньшей мере одна из подложек (2, 13) представляет собой керамическую подложку (10, 17), прежде всего многослойную керамическую подложку (10), полученную методом низкотемпературного спекания сырых пластин (LTCC-подложку), или медно-керамическую ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ОЧИСТКИ, РАЗДЕЛЕНИЯ, МОДИФИКАЦИИ И/ИЛИ ИММОБИЛИЗАЦИИ ХИМИЧЕСКИХ ИЛИ БИОЛОГИЧЕСКИХ ОБЪЕКТОВ, НАХОДЯЩИХСЯ В ТЕКУЧЕЙ СРЕДЕ, И ОПОРА ИЗ МИКРОПРОВОЛОКИ

... 1. Устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством связывания химического или биологического объекта с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаемого между опорами из микропроволоки и частицами, находящимися в текучей среде, на разделение названных частиц, которое содержит по меньшей мере одну опору из микропроволоки, закрепленную своими концами и имеющую многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя и пригодную для связывания химических или биологических объектов, при этом поверхность микропроволоки модифицирована путем присоединения лигандов или нанесением на нее функционального покрытия. ! 2. Устройство по п.1, в котором центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический ...

СПОСОБ ИЗГОТОВЛЕНИЯ ЭЛЕКТРОННЫХ ИЛИ ФУНКЦИОНАЛЬНЫХ УСТРОЙСТВ

... 1. Способ изготовления электронного или функционального прибора с множеством электронных или функциональных устройств на гибкой подложке, включающий в себя этапы обеспечения жесткой подложки, имеющей поверхность нанесения; формирования разделительного слоя на этой поверхности нанесения; нанесения множества областей материала на разделительный слой для создания матрицы устройств; снятия матрицы устройств с поверхности нанесения; прикрепления гибкой подложки к упомянутой матрице. 2. Способ по п.1, в котором по меньшей мере некоторые из упомянутого множества областей материала наносят в виде капель жидкости. 3. Способ по п.1 или 2, в котором этап снятия матрицы устройств с поверхности нанесения происходит после этапа прикрепления гибкой подложки к упомянутой матрице. 4. Способ по п.1 или 2, в котором этап прикрепления гибкой подложки происходит непосредственно после этапа формирования разделительного слоя на поверхности нанесения. 5. Способ изготовления электронного или функционального прибора ...

Halbleiteranordnung mit Metallplatte

VERFAHREN ZUR HERSTELLUNG EINER METALLISIERUNG AUF EINEM SUBSTRAT

Verpackung für elektronische Komponenten

Repeated firing resistant ceramic circuit substrate

A low temperature fired ceramic circuit substrate has laminated insulating layers of ceramic fired at 800-1000 deg C, a silver-based conductive wiring in the inner insulating layer and a gold-based conductive wiring on the surface insulating layer, the novelty being that a metallic interlayer (16), formed from a gold/silver-based thick film paste, is provided between the inner layer wiring (15) and the surface layer wiring (17). Preferably, the gold-silver material contains 10-80 wt.% Au and 90-20 wt.% Ag.

Lichtquelle und Verfahren zur Montage lichtemittierender Dioden

Mit Harz eingekapseltes Halbleiterbauelement

KLEBSTOFFPASTE WELCHE EIN POLYMERES HARZ ENTHÄLT

VERFAHREN ZUM HERSTELLEN EINER SCHALTUNG

A process is disclosed for producing a circuit having a first circuit plane made of a ceramic substrate (1) provided for example with thick film structures and corresponding strip conductors with contact surface (4). The process allows the ceramic substrate to be bonded to a second circuit plane made of a greentape substrate (3). Vias (7) are formed in the greentape substrate and filled with conducting contact material (6), forming complementary contact surfaces (5) to the contact surfaces (4) on the ceramic substrate (1). The contact surfaces (4, 5) are printed with a bonding layer (8) (for example silver or copper paste). The ceramic substrate (1) and/or a lower side of the greentape-substrate is printed with glass ridges (10).

Thixotrope Leiterpaste

Verbesserte Glaskeramik-Kupfer-Verklebung.

LAMINIERTES SUBSTRAT FUER INTEGRIERTE SCHALTUNGEN.

Haft-Klebemittel-Zusammensetzung für Halbleiter.

Gehäuse einer integrierten Schaltung.

Gehäuse einer integrierten Schaltung.

Zusammensetzungen zum Füllen von Durchgangslöchern

LEISTUNGSELEKTRONIKEINHEIT

TANDEM-SOLARMODUL

Bauelement mit empfindlichen Bauelementstrukturen und Verfahren zur Herstellung

Elektrisches Bauelement,- mit einem Substrat, das ein Material mit pyroelektrischen oder piezoelektrischen Eigenschaften umfasst- mit auf der Oberfläche des Substrats angeordneten elektrischen Leiterbahnen (LB) und zumindest drei elektrisch leitenden Bauelementstrukturen (BS1, BS2, BS3), die gegenüber einer Spannung empfindlich oder durch einen elektrischen Überschlag gefährdet sind,- bei dem in einer Vorstufe des Bauelements die zumindest drei Bauelementstrukturen (BS1, BS2, BS3) jeweils über zumindest eine der elektrischen Leiterbahnen (LB) mit einer von zumindest drei elektrischen Anschlussflächen (AF1, AF2, AF3), die von außen zugänglich sind, verbunden sind- bei dem je zwei der Anschlussflächen mittels einer der zumindest zwei Shuntleitungen (SL1, SL2) kurzgeschlossen sind, wobei jede der zumindest zwei Shuntleitungen (SLi, SL2) mindestens einen Abschnitt mit verringertem Querschnitt gegenüber den elektrischen Leiterbahnen aufweist.

Dreischichtige Strahl-MEMS-Einrichtung und diesbezügliche Verfahren

Organischer pixelierter Flächendetektor und Verfahren zu seiner Herstellung

Leiterplatte, Hochfrequenzmodul und Radarvorrichtung

Die Erfindung bezieht sich auf eine Leiterplatte. Die Leiterplatte (10) umfasst ein Substrat (1), eine Wellenleiterleitung (2) und einen laminierten Wellenleiter (3). Die Wellenleiterleitung (2) ist zumindest teilweise auf einer ersten Oberfläche des Substrats (1) angeordnet. Die Wellenleiterleitung (2) überträgt ein Hochfrequenzsignal. Der laminierte Wellenleiter (3) ist innerhalb des Substrats (1) ausgebildet. Der laminierte Wellenleiter (3) ist mit der Wellenleiterleitung (2) elektromagnetisch gekoppelt und weist einen Ausleitungsabschnitt (3a) auf, der vom Inneren des Substrats (1) zu einer anderen Oberfläche als der ersten Oberfläche ausgeleitet ist. Der laminierte Wellenleiter (3) umfasst eine dielektrische Schicht (31), zwei Hauptleiterschichten (32) und eine Durchgangsleitergruppe (33). Die zwei Hauptleiterschichten (32) legt die dielektrische Schicht (31) in einer Dickenrichtung davon ein. In der Durchgangsleitergruppe (34) sind mehrere Durchgangsleiter (33) entlang einer Hochfrequenzsignal-Übertragungsrichtung ...

Designmethode für auf einem Träger angeordnete VLSI-Chips und resultierender Modul

Verfahren zum Herstellen einer Halbleiteranordnung.

Glass ceramic having a specified relative permittivity used in the production of electrical components comprises a ceramic material, and a glass material containing a boron oxide, a silicon oxide, a divalent metal oxide, and a bismuth oxide

Glass ceramic having a relative permittivity of 600-10,000 comprises at least one ceramic material, and at least one glass material containing at least one oxide with boron, at least one oxide with silicon, and at least one oxide with at least one divalent metal Me<2+>. The glass material also has at least one oxide with bismuth. An Independent claim is also included for an electrical component (5) comprising the above glass ceramic. Preferred Features: The divalent metal is beryllium, magnesium, calcium, strontium, barium, copper and/or zinc.

VERFAHREN ZUR HERSTELLUNG VON ÖFFNUNGEN IN EINEM SUBSTRAT, INSBESONDERE VON DURCHGANGSLÖCHERN DURCH EIN SUBSTRAT

Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path

Connection is provided by electrically conductive connection element (11), e.g. bonding wire, which is ultrasonically welded to conductor path (5) applied to surface of glass plate (1) and which is coupled to sensor terminal (13) mounted on glass plate. Surface (3) of glass plate is ridged at point of connection between conductor path and connection element, ultrasonic welding position lying in furrow between 2 ridges (4). An Independent claim for an application of a sensor terminal connection for a ceramic glass cooking hob surface is also included.

Metallisierung für Hohlraumgehäuse und nicht-magnetisches hermetisch dichtes Hohlraumgehäuse

Metallisierung (30) für eine Keramik (10), aufweisend: – eine ein Metall aufweisende Basisschicht (12), – eine Haftschicht (14), wobei die Haftschicht (14) Palladium aufweist und die Schichtdicke der Haftschicht (14) zwischen 0,1 und 5,0 μm beträgt, – eine lötfähige Schicht (16) aus einem nicht ferro-magnetischen Material, wobei sich das Material der Haftschicht (14) vom Material der lötfähigen Schicht (16) unterscheidet, und – eine Oxidationsschutzschicht (20).

Microwave module comprising substrate with HF and LF layers forming distribution network structures, includes intervening insulating layer

The high frequency structure layer (4) is separated from the low frequency structure layer (3) by the insulating layer (1). An Independent claim is included for the method of manufacture, which especially employs fine pitch flip-chip technology for bonding to the substrate.

Sinterwerkstoff, Sinterverbindung sowie Verfahren zum Herstellen eines Sinterverbindung

Die Erfindung betrifft einen Sinterwerkstoff mit metallischen, mit einer organischen Beschichtung versehenen Strukturpartikeln. Erfindungsgemäß ist vorgesehen, dass nicht-organisch beschichtete, metallische und/oder keramische, beim Sinterprozess nicht ausgasende Hilfspartikel (7) vorgesehen sind. Ferner betrifft die Erfindung eine Sinterverbindung (1) sowie ein Verfahren zum Herstellen einer Sinterverbindung (1).

Control unit for motor vehicles braking systems comprises a frame having a recess filled with a sealing gel which is viscous enough the flow around electrical strip conductors in the recess

Control unit (1) comprises a frame (8) having a recess (9) filled with a sealing gel (16) which is viscous enough the flow around electrical strip conductors (10) in the recess. An independent claim is also included for a process for the production of a control unit. Preferred Features: The sealing gel is a silicone gel which remains elastic after hardening. The recess of the frame is formed as a peripheral groove (9). The unit has a base plate (11) made from a conducting material, e.g. a metal.

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG

Laminierte Leiterplatte und Herstellungsverfahren

Halbleiterschaltung

Gehäuseanordnung für elektronische Bauelemente und Verfahren zum Verpacken elektronischer Bauelemente

Gehäuseanordnung für mindestens ein elektronisches Bauelement, mit: – einem Substrat mit einer ersten und einer zweiten Oberfläche, wobei die erste Oberfläche mehrere erste und zweite Kontaktanschlüsse aufweist, die zweite Oberfläche mehrere Verbindungsanschlüsse aufweist und die ersten Kontaktanschlüsse mit den Verbindungsanschlüssen über Durchgangslöcher verbunden sind, – einer elastischen Pufferschicht zwischen der ersten Substratoberfläche und elektronischen Bauelement, wobei eine Oberfläche des elektronischen Bauelementes mit Elektroden gegenüber der ersten Oberfläche des Substrats angeordnet ist, die Pufferschicht mindestens eine Öffnung aufweist, um die mehreren ersten Kontaktanschlüsse freizulassen, die Pufferschicht den Rand des elektronischen Bauelementes umgibt und die einander zugewandten Befestigungsseiten des Randes des elektronischen Bauelementes und der Pufferschicht Schultern und Ecken/Zacken aufweisen und der Rand des elektronischen Bauelementes in die Pufferschicht eingedrückt ...

Thick film circuit board useful as an IC substrate installed in an automobile engine compartment

A circuit board has a conduction suppressing agent between silver-containing wiring portions to prevent conduction in the silver deposited on the substrate between the wiring portions. Independent claims are also included for the following: (i) an insulating paste composition containing a potassium compound; (ii) a conductive paste composition comprising a dispersion of silver-containing metal powder and an inorganic binder in an organic vehicle and which also contains a potassium compound; (iii) a conductive paste composition comprising an organic dispersion of silver-containing metal powder and an inorganic binder formed of a substance which prevents evaporation of the silver from the metal powder; (iv) a conductive paste composition comprising a dispersion of silver-containing metal powder in an organic vehicle; (v) an insulating paste composition which is used between the wiring portions of the above circuit board and which comprises the conduction suppressing agent; (vi) a conductive ...

Assembly structure of electronic parts prevents the formation of cracks in adhesive substrate

The assembly structure has the electronic part (11), which has first and second electrodes (13), a substrate on which the part is mounted, first and second solder eyes (15) on the substrate and a conducting adhesive (16) between the first electrode and first solder eye and between the second electrode and second solder eye to electrically connect them. Part of the conducting adhesive spreads out from one of the electrodes and solder eyes. An Independent claim is also included for a method of assembling electronic parts.

Insulator for supporting thyristor heat dissipating members - has ribbed insulator embedded between tapped metal bush and outer metal ring

The insulator suitable for carrying heat dissipating members for a disc shaped thyristor contains a metal bush (1) into which screws a rod. The bush is mounted on a lower member, and the rod passes through an upper member and carries members which hold down the upper member. The metal bush has a bottom flange (1b), and the whole is embedded in insulating material (3). This material extends above the bush and includes external cooling ribs (3b), while the base is stepped to match the bush inside. This includes a larger diameter portion (3d) which carries an outer metal ring (2) which assists its keying into the lower member. Its top surface is flush with that of the lower member, and the cooling ribs are above it. The metal parts are of non-magnetic metal and the insulating material may be of ceramic or a glass fibre reinforced substance.

Verfahren zum Erzeugen von Lotkontakten für elektrische Bauelemente

Hochfrequenz-Halbleitervorrichtung

Leiterplatte mit verbesserten Positionierungsmitteln

HARZZUSAMMENSETZUNGEN

STEUERGERÄTEEINHEIT UND VERFAHREN ZUR HERSTELLUNG DERSELBEN

Gesinterte Aluminiumnitridkörper und ihr Herstellungsverfahren

VERFAHREN ZUM ABDICHTEN VON UMHUELLUNGEN FUER ELEKTRISCHE TEILE

Manufacturing ceramic multilayer circuit of green ceramic foils

Into the green ceramic foils are stamped through contact apertures (1) and filled with an A6 conductive paste. Then A6 etc. conductive path (2) are printed onto the foils. The ceramic foils are assembled into a stack (3) and interconnected by compression, followed by sintering. During and/or after sintering outer A6 conductive paths (4) and/or contacts (5) are deposited onto the outer sides (10) of the foil stack and a metal protection layer, preferably of Ni and/or Au is coated onto the outer conductive paths and/or contacts, i.e. the latter are first coated with an Ni layer and then with an Au film.

HALBLEITERBAUTEIL

Verfahren zum Verbinden einer Edelmetalloberfläche mit einem Polymer

Verfahren zum Verbinden einer Edelmetalloberfläche eines Halbleitermaterials oder eines Schaltungsträgers mit einem Polymer mit den Schritten:Abscheiden einer Schicht (3) aus 20% bis 40% Gold und 80% bis 60% Silber auf einen Träger,selektives Entfernen des Silbers zur Erzielung einer nanoporösen schwammartigen Goldschicht (4),Auftragen eines flüssigen Polymers, wobei das flüssige Polymer in die nanoporöse schwammartige Goldschicht (4) eindringt und eine dreidimensionale Grenzfläche mit mechanischer Verzahnung zwischen der nanoporösen schwammartigen Goldschicht (4) und dem flüssigen Polymer gebildet wird,Aushärten des flüssigen Polymers zur Erzeugung einer Polymerschicht (5).

Multilayer circuit module for wireless communication system has passive high frequency components and passive base component layer

A connection integration region includes at least one connecting layer (404,408) for electrically coupling the circuit components (409). A passive base component integration region has a passive base component layer (405,407). A passive high frequency component integration region comprises passive high frequency components. An Independent claim is included for a method of manufacturing a multilayer circuit module.

Coil isolators

PROCESS FOR FABRICATING A SEALED ELECTRIC CONDUCTIVE PASSAGE IN AN INSULATOR AND AN INSULATOR CONTAINING THE SAME

... 1457247 Printed circuit assemblies SOC SUISSE POUR L'INDUSTRIE HORLOGERE (SSIH) MANAGEMENT SERVICES SA 28 April 1975 [20 May 1974] 17528/75 Heading H1R An insulant plate of ceramic material containing a metallic oxide is subjected to a zonal chemical reduction process on each side so that the reduced zones coalesce to establish electrical connections therethrough; the zones being defined by masks (Fig. 1, not shown). The zones to be reduced 3 (Fig. 2) may be of lesser thickness and the entire surface of the plate 1 is reduced to produce a surface conducting layer 2 which may be generally or selectively polished or milled off (Fig. 3). The through connection zones may be interconnected by conductors formed by selective surface reduction (Fig. 4, not shown). The connection zones may be metallized at 5 (Fig. 5) and conductive members may be soldered or welded thereto at 8. An encapsulation may be welded or soldered to reduced areas of the edges of the plate 1. The ceramic material may be TiO ...

Surface mount spark gap

Improvements in semiconductor devices

... 1,106,787. Transistors. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 15 April, 1965 [21 April, 1964], No. 16248/65. Heading H1K. A transistor comprises a semi-conductor wafer with an elongated base region 2 at one surface (Fig. 1), an emitter region within it comprising a main part near one end of the base region and an extension 4 to one side of the base region, and a base contact 9 between the extension and the other side of the base region. The regions and contacts may have rounded corners if desired. Although the base and emitter regions may be produced by epitaxial deposition it is preferred to form them by diffusion through oxide masking prepared by photolithographic techniques. The main wafer is N-type silicon and the diffusants boron and phosphorus respectively. The contacts, formed by evaporation, may be extended at 11, 12 over the oxide to the edges of the wafer. A plurality of the transistors may be formed simultaneously in a wafer from which they are subsequently subdivided ...

Improvements in hybrid microcircuits

... 1,126,986. Semi-conductor devices; circuit assemblies. SOC. EUROPEENNE DES SEMICONDUCTEURS. 2 May, 1966 [30 April, 1965], No. 19250/66. Headings H1K and H1R. A hybrid microcircuit is made by depositing passive components and conductors 6, 9 on one face of a first insulating plate 19, and locating semi-conductor devices such as transistors 1, 2 in cavities 21, 22 in a second insulating plate 20; the two plates 19, 20 are placed together, planar terminal areas on devices 1, 2 being, urged against connection areas on plate 19 by molybdenum springs 23, 24 in cavities 21, 22, and the plates are sealed together by. the insertion of a peripheral frame 25, of, e.g. "Kovar" (Registered Trade-Mark), followed by heating in a rare gas atmosphere. A plurality of "Kovar" tapes (or wires) 13 are sealed through plate 19, which may be of glass or ceramic, preferably during the formation of. the plate, and are levelled off flush with the internal face of the plate. The invention is described with reference ...

ENCAPSULATED MICROCIRCUIT DEVICE

... 1,269,341. Semi-conductor devices. WESTINGHOUSE ELECTRIC CORP. 18 March, 1969 [21 March, 1968], No. 14105/69. Heading H1K. A semi-conductor device comprising a wafer of semi-conductor material having a contact pattern surrounded by a layer of alumina is provided with at least one film of silica glass doped with an oxide of at least one of the elements boron, arsenic and phosphorus. In a first embodiment, Fig. 1 (not shown), an integrated circuit having a surface layer of Al 2 O 3 over which extend conductors is encapsulated by a glass layer through which are formed windows to expose areas of the conductors. In a second embodiment, Fig. 2 (not shown), a silicon dioxide layer is covered with a layer of alumina over which first level connections are formed. A glass layer is deposited, windows are formed, and second level connections are formed, which are themselves covered with a glass layer. The glass layer may be produced by thermal decomposition of tetraethoxysilane, Si(OC 2 H 5 ) 4 , in ...

SEMICONDUCTOR DEVICES

... 1299514 Semi-conductor devices GENERAL ELECTRIC CO 3 Feb 1970 [3 Feb 1969 (2)] 5182/70 Heading H1K In a semi-conductor device adapted to be mounted under compression one major surface of a semi-conductor wafer 102 carries a thin Al coating 148, and a low thermal expansion coefficient (less than 10-5 per ‹C.) "back-up plate" 152 is mounted between, but not bonded to, the Al coating 148 and a terminal member 158 forming part of one end wall of a housing for the device. The housing includes a ceramic or glass ring 122 sealed at both ends by metal diaphragms 120, 168 carrying the terminal members 118, 158, which may be made of brass, Cu or Al. The back-up plate 152 may be of W or Mo carrying a malleable layer 154. The device shown is a Si thyristor having a central gate region 106a connected to a sprung lead 142 which passes through a slot 160 in the terminal member 158 and is insulated therefrom by an insulating lining 162 in the slot 160. An insulating ring 164 surrounds the end ...

Electrically isolated power semiconductor package

Hybrid laminate

A hybrid laminate comprises: a substrate layer containing a compact of first powders; and a functional material layer being in contact with the substrate layer and containing a compact of second powders; wherein the compact of the first powders comprises a glass material; the compact of the second powders comprises a ceramic material having at least one specific electric property selected from dielectricity, magnetism, resistivity and insulation; at least a part of the first powders is in a sintered state; and the second powders are in an unsintered state and are bonded together by diffusion or a flow of a part of the material of the substrate layer into the functional material layer.

Surface acoustic wave device and method for making the same

SOLDERABLE ADHESIVE LAYER

LOW TEMPERATURE GLASS COMPOSITION,PASTE AND METHOD OF USE.

A stable Tl2O3, V2O5, P2O5 glass composition for a die attach paste requiring no resin and having a glassy edge temperature of below about 350 DEG C.

ELECTRICALLY INSULATING CERAMIC MATERIAL

A ceramic material having a dieiectric constant of less than 6 when measured at 1 MHZ is formed by preparing a green structure composed of foam and alumina having a surface area of 20M/g and glass frits powder. A laminate of three 1.016mm layers of the green structure is then sintered in air at about 920 DEG C to gild the ceramic material.

Composite monolithic electronic component

Laminated interconnects for opto-electronic device modules

A method of producing an encapsulated module of interconnected opto-electronic devices such as organic photovoltaic (PV) devices or organic light emitting diode (OLED) devices is provided, which comprises: forming a patterned anode layer 104; forming a layer of opto-electronically active material 108 over the patterned anode layer 104; forming a patterned cathode layer 110 over the layer of opto-electronically active material 108, to provide a device array 100 of opto-electronically active cells on the substrate; selectively removing portions of the layer of opto-electronically active material 108 so as to expose minor portions 104a of the anodes 104; forming a patterned interconnect layer 171 on an encapsulating sheet 172 in a pattern to define an array of interconnect pads 171; and laminating the patterned encapsulating sheet 170 over the array 100 of opto-electronically active cells whereby the exposed anode portions 104a are interconnected with the cathodes 110 of adjacent cells by ...

Method of producing a microminiaturised circuit arrangement

... 1,110,587. Circuit assemblies; semi-conductor devices. TELEFUNKEN PATENTVERWERTUNGS-G.m.b.H. 21 July, 1965 [29 July, 1964; 23 Nov., 1964]. No. 31021/65. Headings H1K and H1R. In a method of making a microminiature circuit assembly, a solid state circuit produced in a semi-conductor body is attached to a selfsupporting insulating substrate, after which the individual devices comprised within the solid state circuit are separated from one another by the removal of semi-conductor material to avoid capacitive coupling. The solid state circuit may comprise an insulating passivation layer on the surface which is attached to the substrate, and a further passivation layer may be applied to the complete assembly. The insulating substrate may comprise a sintered, melted, or vapour-deposited layer of glass, or a ceramic body 9, Fig. 4, having a surface glaze 14, which is attached, directly or by means of a layer 15 of insulating solder, to a solid state circuit 16 having a passivation surface layer ...

THERMAL HEAD DEVICE

Header for a Semiconductor Device

... 1,168,345. Headers for semi-conductor devices. TEXAS INSTRUMENTS Inc. 14 Feb., 1967 [28 Feb., 1966], No. 7037/67. Heading H1K. A header for a semi-conductor device is formed by coating a wire 1 with brazing material 2, placing it in a header eyelet 11 so that it abuts a surface of the eyelet, inserting at least two more wires 15, 16 through holes in the eyelet, filling the eyelet with insulating material 10, e.g. a glass preform, and heating the assembly to braze the wire 1 to the eyelet 11 and to melt the insulation 10 around the wires. The brazing material 2, which may be Ag or a Ag/Cu alloy, may be coated on the wire 1, which may be of a Ni/Fe/Co alloy and which may be nickelplated, by plating, electrodeposition or by melting a ball of the material 2 in contact with the wire 1. Preferably all three wires and the eyelet 11 are Au-plated. A graphite jig is provided to support the assembly during heating.

Integrated circuit packages

Integrated circuit package

A hermetically sealed integrated circuit package having a rectangular base member and a similar frame member 11, the frame 11 having an internal feature X positionally related to the adjacent external corner Y to a very high degree of accuracy. The external dimensions of frame 11 are slightly larger than those of the rest of the package so that when the package is assembled corner Y stands proud of the rest of the package 13. This enables an internal element of the packaged chip to be located accurately. ...

LEADED CHIP CARRIER

Cooling semiconductor devices with flowing fluid

A water cooled heat sink particularly for use with traction power semiconductor comprises a plate like body having channels in both faces separated by a central partition but forming a common circulatory channel. The channels are of spiral form the walls separating adjacent channels providing a support for a 'lid' which is sealed to each face. Water is then pumped through the channels, in contact with the 'lids' from an inlet to an outlet port. The 'lids' are formed by composite tiles, each consisting of a wafer of ceramic of good thermal conductivity, having on both sides a layer of copper intimately bonded to it. Maximum heat transference ability is achieved by the thin-ness of the tile and the channel structure, while maintaining the necessary electrical insulation.

Device for regulating the working depth of an implement connected to a tractor

... 954,491. Tractor power lift mechanisms. MASCHINENFABRIK FAHR A.G. June 2, 1960, No. 19540/60. Heading A1P. A feeler device for regulating the working depth of an implement attached to a tractor by a conventional three point power lift linkage comprises a roller 6 carried by a lever 7 pivoted to the implement at 16 and operating upon the control member of the power lift through a system of levers 8, 9, 10, bell crank 9a, 21, and a spring loaded sliding member 11. The bell crank 9a, 21 is connected to the lever 9 by a screw 25 which permits adjustment. Stops 26 and 27 limit the upward movement of the lever 7 and facilitate carrying the feeler in a transport position.

Insulating ceramic multilayer ceramic substrate ceramic electronic parts and laminated ceramic electronic parts

Improvements in or relating to semiconductor devices

... 1,036,165. Semi-conductor devices. STANDARD TELEPHONES & CABLES Ltd. Jan. 29, 1964, No. 3786/64. Addition to 1,023,531. Heading H1K. A device comprising a semi-conductor wafer with at least one contact comprising a layer grading outwards from an adherent to a softsolderable metal and extending from a semiconductor zone on one face over an insulating layer thereon has its contacts soldered to the lead wires of a header. In an embodiment, a planar transistor, Fig. 1, made in multiple by successive diffusions into a silicon wafer through apertures formed in a surface oxide layer by photo-resist etching techniques, is provided with an overall film of aluminium. This is removed, except from areas of the emitter, base and collector zones exposed through apertures in the oxide film, by photo-resist etching techniques. An overall film graded from chromium beneath to gold above is then deposited as described in Specification 1,010,111 and reduced to strips 9, 10, 11 in contact through the aluminium ...

Flip-chip stress aborbing layers and connections

A resin coated conductor (RCC) structure 34', 35 having a stress relieving photosensitive layer 34' is formed over a stress relieving thermosetting insulating layer 34. Flexible contacts 38 may be formed using metallic powders or wirebonds. Arrangements are also described which only use a stress relieving layer on the RCC structure and without a stress relieving thermosetting layer formed directly on the substrate (figures 9A-C and 10A-C). Delamination of the flip-chip device mounted on a circuit board having a differing thermal expansion coefficient is reduced.

A semi-conductor device

... 969,587. Semi-conductors. SIEMENSSCHUCKERTWERKE A.G. Aug. 13, 1962 [Aug. 12, 1961], No. 31045/62. Heading H1K. A semi-conductor device has a semi-conductor body adjacent a further body of different thermal coefficient of expansion with means for urging the bodies together so that on heating one body slides with respect to the other, the contacting and mutually sliding surfaces being of silver and nickel respectively. In the embodiment a semi-conductor rectifier element 7, e.g. of silicon, having a layer of silicon and a layer of nickel on each surface, rests on the silvered base4 of a copper container 1. The domed end 9b of a copper terminal member is urged against the element by the dished springs 12-14 mounted on an insulating body 10 and the apparatus is heated for a period causing the outer silver layer 8 on the element 7 to fuse into the surface of the dome 9b so that sliding occurs between the silver and nickel layer on the element 7. The coatings on the element 7 may be applied by ...

Improvements in or relating to glassy compositions

... A single phase glassy composition comprises a first component consisting of arsenic or arsenic containing at least one of the elements antimony and bismuth, a second component consisting of sulphur or sulphur containing at least one of the elements selenium and tellurium, a third component consisting of iodine, or bromine or iodine and bromine, or iodine and/or bromine containing at least one of the elements fluorine and chlorine, with or without a fourth component consisting of at least one of the elements lead, gallium, indium and thallium, the balance, if any, consisting of other compatible components. Fig. 1 gives the range of compositions of the As-S-I system, the I being replaceable by Br, these systems giving the preferred compositions. Up to 20 mol. per cent of the S and As may be replaced by respectively Se and/or Te and Sb and/or Bi. As shown in Fig. 5C, a diode device 40 is encapsulated by molten glasseous material 48 ...

A semiconductor device and method of making

... 1,069,506. Semi-conductor devices. NORTH AMERICAN AVIATION Inc. Feb. 8, 1966, No. 5410/66. Heading H1K. A method of making a semi-conductor device in a thin film of monocrystalline semi-conductor material bonded to an insulating substrate comprises masking the surface of the film and diffusing impurity completely through at least two regions of the film to alter its conductivity. A thin film is defined as having a thickness of 50 Š to 3 Á. A plurality of insulated gate F.E.T.'s are produced by epitaxially growing a thin film of P-type silicon doped with boron on a sapphire substrate 20, polishing the surface of the film, oxide masking and etching to divide the film into a plurality of strips 21, bevelling the edges of the strips by mechanical polishing, Fig. 5 (not shown), covering strips 21 with a thermally grown layer of silicon dioxide, masking and etching this oxide layer to form a plurality of strips (25) extending transversely to strip 21, Fig. 4 (not shown), and diffusing boron into ...

COMPOSITIONS AND CERAMIC ARTICLES COMPRISTING THEM

A semiconductor device and a method for its production

A semiconductor device wherein a coating film which is made of a polyimide resin or a polyimide isoindoloquinazolinedione resin and which is at least 10 mu m thick is disposed on at least an active region of a semiconductor substrate, and the resultant semiconductor substrate is encapsulated in a ceramic package. The semiconductor device has troubles relieved conspicuously, the troubles being ascribable to alpha-rays which come flying from impurities contained in the material of the package.

SEMICONDUCTOR DEVICE WITH REGISTRATION MARK FOR ELECTRON BEAM EXPOSURE

METALLIC LEADS FOR ELECTRONIC DEVICES

... 1331901 Component assemblies; semi-conductor devices E I DU PONT DE NEMOURS & CO 4 Feb 1972 [5 Feb 1971] 5408/72 Headings H1K and H1R [Also in Division H2] In a semi-conductor device package, the thick film material substrate 8 is connected to metallic leads 2, by means of a clamp portion 3. Bifurcated fingers 4 and 5 clamp the lead to the terminal 9, and are soldered thereto, and laterally disposed offset tab 7 is adapted to abut the clamp 3 at a predetermined distance from the substrate. In Fig. 3, an adaptation with only two of the described leads 11 is shown. The nature of the clamp is to maintain a rigid bond at the high temperatures required for the use of thick film materials in the insulating dielectric, 13, substrate 8, metallurgical seal ring 12, conducting fingers 14 semi-conductor die attachment region 15, and terminal pads 9, the assembly may then be hermetically sealed. An elongated shorting or tie bar 1 is provided to maintain the leads 2 in proper relationship to each other ...

LEADED CHIP CARRIER

Multilayer circuit component and method for manufacturing the same

MANUFACTURE OF INTEGRATED CIRCUITS

... 1,221,914. Circuit assemblies. STANDARD TELEPHONES & CABLES Ltd. 13 June, 1969, No. 30065/69. Heading HlR. In the manufacture of a hybrid circuit module, monolithic integrated circuit chips 11 are bonded in holes in a substrate, which may or may not be provided with the conductor pattern of the circuit, and a conducting pattern is deposited between terminals 14 on each of the chips and the substrate. In one method, the substrate, e.g. of glass or ceramic, is first provided with a first pattern of conductors, e.g. by evaporation, a dielectric layer 6 is then applied with appropriately spaced windows, a second pattern of conductors 10 is deposited so as to complete the conductor pattern of the circuit, the chips are bonded in the holes, and finally a conductor pattern 13 interconnecting terminals 14 on the chips to terminals 5 on the substrate is deposited, e.g. by evaporation and photographic techniques. Alternatively, the chips are first bonded in the holes and the conductor pattern is ...

SEMICONDUCTOR DEVICE

... 1,264,055. Semi-conductor devices. LICENTIA PATENT-VERWALTUNGS G.m.b.H. 17 March, 1970 [21 March, 1969], No. 12838/70. Heading H1K. A semi-conductor device such as a power transistor 17 is mounted on an insulating plate 2 which in turn is mounted on a metal plate 1. Two metallized areas 5, 6 on the insulating plate 2 extend across the edges of the plate 2 to contact the metal plate 1 while two further metallized areas 7, 8 on the plate 2, one of which areas 8 extends between the first two areas 5, 6, carry terminal strips 3, 4. The electrodes of the device 17 are connected to the metallized areas 5-8. In the preferred embodiments the collector of the transistor is mounted directly on the area 8, parallel wires 20 being used to connect the base electrode 18 to the area 7 and the emitter electrode or electrodes 19 to the areas 5, 6. A modified metallization pattern is also described. The metal plate 1 may be of Mo or vacon, the insulating plate 2 being of beryllium oxide and the metallized ...

Solder connect assembly and method of connecting a semiconductor package and a printed wiring board

CIRCUIT ASSEMBLIES

... 1498637 Electrical connectors SIEMENS AG 24 Oct 1975 [6 Dec 1974] 43722/75 Heading H2E [Also in Division H1] Wire bridges 11 are soldered between the contact arms 8a and 8c, or 8b and 8d, extending from the contact elements 5 which are soldered to the electrodes 6, to switch off, or switch on, the attenuation T-element formed by film circuit resistances 2a, 2b, 2c on the glass or ceramic substrate 3. Contact arm 8 and resistance 2 are part of the next attenuation element on the substrate. Cross pieces 13, 15, which facilitate connection of the contact elements to the substrate, are removed after soldering of the latter, the rods 7 then being inserted through holes in a carrier plate for soldering to printed circuit paths thereon.

Semiconductor diodes

... 895,232. Semi-conductor diodes. HACKBRIDGE & HEWITTIC ELECTRIC CO. Ltd., WELLS, R., and FRICKER, D. J. July 21, 1960 [Aug. 11, 1959], No. 27424/59. Class 37. A diode comprises a PN semi-conductor body mounted on a solid projection in a cup-shaped terminal member which together with a second cup - shaped terminal member forms a sealed enclosure. Fig. 2 shows a semi-conductor body 20 comprising a PN junction, opposite faces being connected to two cup-shaped metal terminals A and C, which are hermetically sealed together by an insulating material such as " Araldite " (Registered Trade Mark). An L-shaped ring 13 may be provided, so that during assembly, ring 13 is first placed on an insulating support inside the flange of terminal C, the semi-conductor body is placed on the central extension of terminal C which extends beyond the flange portion of terminal C. Terminal A is then placed in position and the insulating resin applied to terminals A and C and ring 13. The semi-conductor body is first ...

PACKAGE FOR HERMETICALLY SEALING ELECTRONIC CIRCUITS

... 1514595 Electric circuit assemblies HUGHES AIRCRAFT CO 9 Feb 1976 [3 March 1975] 04946/76 Heading H1R A module 10 (Fig. 1) supporting an integrated circuit wafer 12 is supported on a substrate 14 (Figs. 2a, 2b) of, e.g. ceramic material, which comprises a printed circuit board with radial leads 16 or pins 18 intersecting the base. Exterior leads 24 connect these to a multipin plug connector 26 connecting to a system (not shown). Substrate 14 is, e.g. adhesively bonded to frame 30 screwed to connector 26. A cooling fan system (not shown) is carried by the reverse side of the substrate. A sealing ring 34 is hermetically bonded to a metallized area of the substrate and has a sealing area 38 to which a lid 40 is hermetically bonded to form a sealed package. This may take the form of a ceramic ring 42 (Figs. 2a, 2b) brazed at 44 to substrate 14; and metallised at 46 for brazing to a metal ring 48 extending upwardly to define a sealing area 52 for ceramic lid 54 resting on surface 50 of ring ...

Improvements in or relating to containers including desiccants

... 795,113. Drying - agents. STANDARD TELEPHONES & CABLES, Ltd. June 3. 1955 [June 7, 1954], No. 15973/55. Drawings to Specification. Class 34(1) [Also in Group XXXVI] A material to be permanently kept dry is hermetically sealed in a container with a finely divided dispersion in an inert non- polar liquid of a substance which is non deteriorating to said material and combines chemically and irreversibly with moisture. The substance may be any of the alkali metals or their hydrides, but sodium dispersed in polymethyl siloxane is preferred. The dispersion is obtained by heating Na above its melting point with the siloxane and stirring while it cools. Toluene, silicone oil or fiuorcarbon oils may be used in place of polymethly siloxane. In the embodiments the material to be kept dry is a semi-conductor crystal forming part of a diode or transistor (see Group XXXVI) and the dispersion may be applied either direct to the crystal, to a porous layer on the crystal or to an interior wall of the casing ...

Improvements in semi-conductor devices

... 789,675. Semi-conductor devices. PHILIPS ELECTRICAL INDUSTRIES, Ltd. Dec. 22, 1954 [Dec. 22, 1953], No. 37112/54. Class 37. In a semi-conductor device comprising a semi-conductor body in an envelope formed at least partly of glass or ceramic, a plurality of leads each consisting of an integral conductor are sealed through this part of the envelope. The major portion of the part of each conductor which is inside the envelope is made of reduced section. In the embodiment a series of leads 5 is sealed through glass cover 6, each lead consisting of copper coated nickel-iron wire. The ends of the leads which are to be in the envelope are dipped in an etchant, e.g. dilute nitric acid to remove the copper coating. They are then soldered to the fused-on electrodes of transistor 1 and the latter immersed in a filler e.g. of polymethyl siloxanes in metal tube 8 the flange of which is then sealed to the cover 6 by means of a glaze. The leads may alternatively be of nickel-iron alloy throughout but ...

SEMI-CONDUCTOR ASSEMBLY

Surface mounted led structure and packaging method of integrating functional circuits on a silicon

The present invention relates to a surface mounted LED structure of integrating functional circuits on a silicon substrate, comprising the silicon substrate and an LED chip. Said silicon substrate has an upper surface of planar structure without grooves. An oxide layer covers the upper surface of the silicon substrate, and metal electrode layers are arranged in the upper surface of the oxide layer. The upper surfaces of said metal electrode layers are arranged with metal bumps, and the LED chip is flip-chip mounted to the silicon substrate. Two conductive metal pads are arranged on the lower surface of said silicon substrate, said conductive metal pads are electrically connected to the metal electrode layers on the upper surface of the silicon substrate by a metal lead arranged on the side wall of the silicon substrate. A heat conduction metal pad is arranged on the corresponding lower, surface of the silicon substrate just below the LED chip. Peripheral functional circuits required by LED are integrated on the upper surface of said silicon substrate. The structure of the present invention has advantages of good heat dissipation effect and small volume, and direct integration of functional circuits such as protection and drive circuits etc. in the silicon substrate achieves large-scale production package of wafer level, reducing the cost of packaging and lighting fixture.

Gain Enhanced LTCC System-on-Package for UMRR Applications

An apparatus, system, and method for Gain Enhanced LTCC System-on-Package radar sensor. The sensor includes a substrate and an integrated circuit coupled to the substrate, where the integrated circuit is configured to transmit and receive radio frequency (RF) signals. An antenna may be coupled to the integrated circuit and a lens may be coupled to the antenna. The lens may be configured to enhance the gain of the sensor.

Thermal expansion suppressing member and anti-thermally-expansive member

Provided are a thermal expansion suppressing member having negative thermal expansion properties and a metal-based anti-thermally-expansive member having small thermal expansion. More specifically, provided are a thermal expansion suppressing member, including at least an oxide represented by the following general formula (1), and an anti-thermally-expansive member, including a metal having a positive linear expansion coefficient at 20° C., and a solid body including at least an oxide represented by the following general formula (1), the metal and solid being joined to each other: (Bi 1-x M x )NiO 3 (1) where M represents at least one metal selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y, and In; and x represents a numerical value of 0.02≦x≦0.15.

Image Sensor Package with Dual Substrates and the Method of the Same

The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.

Inductive getter activation for high vacuum packaging

An approach to activating a getter within a sealed vacuum cavity is disclosed. The approach uses inductive coupling from an external coil to a magnetically permeable material deposited in the vacuum cavity. The getter material is formed over this magnetically permeable material, and heated specifically thereby, leaving the rest of the device cavity and microdevice relatively cool. Using this inductive coupling technique, the getter material can be activated after encapsulation, and delicate structures and low temperature wafer bonding mechanisms may be used.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Chip stacked structure

A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

Thermosetting resin composition for sealing packing of semiconductor, and semiconductor device

A thermosetting resin composition for an underfilling of a semiconductor comprising, as essential components, a thermosetting resin, a curing agent, a flux agent and two or more inorganic fillers with different mean particle sizes, wherein the inorganic fillers include an inorganic filler with a mean particle size of no greater than 100 nm and an inorganic filler with a mean particle size of greater than 100 nm.

Through wiring substrate and manufacturing method thereof

A through wiring substrate includes a substrate having a first face and a second face; and a through-wire formed by filling, or forming a film of, an electrically-conductive substance into a through-hole, which penetrates between the first face and the second face. The through-hole has a bend part comprising an inner peripheral part that is curved in a recessed shape and an outer peripheral part that is curved in a protruding shape, in a longitudinal cross-section of the through-hole, and at least the inner peripheral part is formed in a circular arc shape in the longitudinal cross-section.

Thermal Power Plane for Integrated Circuits

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

Ceramic/metal composite structure and method of manufacturing the same

A ceramic/metal composite structure includes an aluminum oxide substrate, an interface bonding layer and a copper sheet. The interface bonding layer is disposed on the aluminum oxide substrate. The copper sheet is disposed on the interface bonding layer. The interface bonding layer bonds the aluminum oxide substrate to the copper sheet. Some pores are formed near or in the interface bonding layer. A porosity of the interface bonding layer is substantially smaller than or equal to 25%. A method of manufacturing the ceramic/metal composite structure is also provided.

Underfill method and chip package

A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Copper conductor film and manufacturing method thereof, conductive substrate and manufacturing method thereof, copper conductor wiring and manufacturing method thereof, and treatment solution

Provided are a copper conductor film and manufacturing method thereof, and patterned copper conductor wiring, which have superior conductivity and wiring pattern formation, and with which there is no decrease in insulation between circuits, even at narrow wiring widths and narrow inter-wiring spacing. Disclosed are a copper conductor film and manufacturing method thereof in which a copper-based particle-containing layer, which contains both a metal having catalytic activity toward a reducing agent and copper oxide, is treated using a treatment solution that contains a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complex to form metallic copper in a single solution, and patterned copper conductor wiring that is obtained by patterning a copper-based particle-containing layer using printing and by said patterned particle-containing layer being treated by a treatment method using a solution that contains both a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complexes to form metallic copper in a single solution.

Semiconductor package and manufacturing method therefor

According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Method of Manufacturing a Printable Composition of a Liquid or Gel Suspension of Diodes

An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary method of making a liquid or gel suspension of diodes comprises: adding a viscosity modifier to a plurality of diodes in a first solvent; and mixing the plurality of diodes, the first solvent and the viscosity modifier to form the liquid or gel suspension of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

Thermally and dimensionally stable polyimide films and methods relating thereto

The present disclosure is directed to a polyimide film. The film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Coverlay compositions and methods relating thereto

The present disclosure is directed to a coverlay comprising a polyimide film and an adhesive layer. The polyimide film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Wiring substrate and method of manufacturing the same

A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.

Sensor module, sensor device, method for producing sensor device, and electronic apparatus

A sensor module includes a supporting member having three support faces orthogonal to one another, three IC chips each having connection terminals and external connection terminals on the side thereof where an active face is located, the three IC chips attached to the support faces of the supporting member on the sides thereof where passive faces lying along the active faces are located, three vibrating gyro elements each having a base, vibrating arms extending from the base, and connection electrodes, and flexible wiring substrates connected to the external connection terminals of the IC chips, each vibrating gyro element is disposed on the side of the IC chip where the active face is located, the connection electrodes are attached to the connection terminals of each IC chip such that one principal surface lies along the support face, and the flexible wiring substrate has a reinforcing layer.

Integrated circuit package including miniature antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

Sensor mounted in flip-chip technology on a substrate

The sensor assembly comprises a substrate ( 1 ), such as a flexible printed circuit board, and a sensor chip ( 2 ) flip-chip mounted to the substrate ( 1 ), with a first side ( 3 ) of the sensor chip ( 2 ) facing the substrate ( 1 ). A sensing area ( 4 ) and contact pads ( 5 ) are integrated on the first side ( 3 ) of the sensor chip ( 2 ) and located in a chamber ( 17 ) between the substrate ( 1 ) and the sensor chip ( 2 ). Chamber ( 17 ) is bordered along at least two sides by a dam ( 16 ). Underfill ( 18 ) and/or solder flux is arranged between the sensor chip ( 2 ) and the substrate ( 1 ), and the dam ( 16 ) prevents the underfill from entering the chamber ( 17 ). An opening ( 19 ) extends from the chamber to the environment and is located between the substrate ( 1 ) and the sensor chip ( 2 ) or extends through the sensor chip ( 2 ).

Stacked electronic component and manufacturing method thereof

A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

Semiconductor device structures

The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

Module substrate, module-substrate manufacturing method, and terminal connection substrate

In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

Heating apparatus and annealing apparatus

A heating apparatus includes a heat dissipating board formed of a metal; an insulating layer directly formed on the heat dissipating board; a plurality of wiring elements which are arranged on the insulating layer in a wiring pattern; and a plurality of LED elements provided on the wiring elements, respectively. The heating apparatus further includes metal wiring lines which electrically connect the adjacent LED elements to each other in series.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Fabrication method of packaging substrate having through-holed interposer embedded therein

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Surface acoustic wave device and production method therefor

A surface acoustic wave device includes a surface acoustic wave element including a plurality of electrode pads, and a mount substrate. The surface acoustic wave element is flip-chip mounted on a die-attach surface of the mount substrate by bumps made of Au. The mount substrate includes at least one resin layer including via-holes, a plurality of mount electrodes provided on the die-attach surface of the mount substrate, and via-hole conductors. The mount electrodes are bonded to the electrode pads via the bumps. The via-hole conductors are provided in the via-holes. At least one of each of the electrode pads and each of the mount electrodes includes a front layer made of Au. At least one of the via-hole conductors is located below the corresponding bump.

Electronic component and method for producing same

This electronic component is provided with an inorganic substrate, a conductor film formed on a surface of the substrate, and bonding wires bonded to a part of said conductor film, and wire bonding sections are formed on at least a part of the electronic component. The part of the conductor film at least forming the aforementioned wire bonding sections contains an Ag-based metal formed of Ag or an alloy having Ag as the main constituent and a metal oxide which coats said Ag-based metal and which has, as a constituent element, any of the elements selected from the group consisting of Al, Zr, Ti, Y, Ca, Mg, and Zn. The coating quantity of the metal oxide is a quantity corresponding to 0.02 to 0.1 parts by mass relative to 100 parts by mass of the aforementioned Ag-based metal.

Stacked semiconductor apparatus, system and method of fabrication

A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

Method for manufacturing semiconductor apparatus

A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; and forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices.

Fixing material comprising silane compound polymer and photonic device sealed body

A fixing material includes a silane compound polymer as the main component, the silane compound polymer being produced by condensing a silane compound mixture that includes at least one silane compound (1) shown by the following formula (1): R 1 Si(OR 2 ) p (X 1 ) 3-p (wherein R 1 represents a group including an ester structure or a cyanoalkyl group, R 2 represents an alkyl group having 1 to 6 carbon atoms or the like, X 1 represents a halogen atom, and p is an integer from 0 to 3), and at least one silane compound (2) shown by the following formula (2): Si(OR 3 ) q (X 2 ) 4-q (wherein R 3 represents an alkyl group having 1 to 6 carbon atoms, X 2 represents a halogen atom, and q is an integer from 0 to 4). A sealed optical device includes an optical device that is sealed with a cured product of the fixing material. The fixing material produces a cured product that exhibits high hardness, excellent transparency and heat resistance, and rarely undergoes coloration even when subjected to high-energy light or heat for a long time.

Film forming method and processing system

A film forming method performs a film forming process on a target object having on a surface thereof an insulating layer. The film forming method includes a first thin film forming step of forming a first thin film containing a first metal, an oxidation step of forming an oxide film by oxidizing the first thin film, and a second thin film forming step of forming a second thin film containing a second metal on the oxide film.

Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same

Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Package-in-Package Using Through-Hole Via Die on Saw Streets

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Semiconductor device structures and printed circuit boards comprising semiconductor devices

The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

Electronic component element housing package

An electronic component element housing package is produced by firing a ceramic substrate for housing an electronic component element and a metal layer for bonding to the ceramic substrate to form an electrical path, simultaneously in a reducing atmosphere. The ceramic substrate comprises alumina (Al 2 O 3 ), a partially stabilized zirconia by forming solid solution with yttria (Y 2 O 3 ) and a sintering agent. The sintering agent comprises magnesia (MgO), and at least 1 type selected from silica (SiO 2 ), calcia (CaO), or manganese oxides (MnO, MnO 2 , Mn 2 O 3 , Mn 3 O 4 ).

Thin film forming method

A thin film forming method in which a thin film is formed on a surface of a target object to be processed to fill a recess formed in the surface of the target object includes the steps of forming a metal layer for filling on the surface of the target object to fill the recess formed in the surface of the target object and forming a metal film for preventing diffusion on an entire surface of the target object to cover the metal layer for filling. The thin film forming method further includes the step of annealing the target object having the metal film for preventing diffusion formed thereon.

Semiconductor device

A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.

Semiconductor Package and Method of Manufacturing the Same

A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

Method for forming a copper wiring pattern

There is provided a method wherein a surface treating agent, which is essential for making copper particles antioxidative and dispersing the copper particles in the prior art, is hardly used, but copper particles, which cause little electromigration and are small in the price rate of material itself, are used to form a low-resistance copper wiring pattern while the generation of cracks therein is restrained. The method includes the step of using a dispersion slurry wherein copper based particles having a copper oxide surface are dispersed to form any pattern over a substrate, and the step of reducing the copper oxide surface of the copper based particles in the pattern with atomic form hydrogen to return the oxide to copper, and sintering particles of the copper metal generated by the reduction and bonding the particles to each other.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Substrate for semiconductor package and method of manufacturing thereof

Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.

Package substrate and die spacer layers having a ceramic backbone

A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

Miniature Surface Mount Device

A surface mount LED package includes a lead frame carrying a plurality of LEDs and a plastic casing at least partially encasing the lead frame. The lead frame includes an electrically conductive chip carrier and first, second, and third electrically conductive connection parts separate from the electrically conductive chip carrier. Each of the first, second and third electrically conductive connection parts has an upper surface, a lower surface, and a connection pad on the upper surface. The plurality of LEDs are disposed on an upper surface of the electrically conductive chip carrier. Each LED has a first electrical terminal electrically coupled to the electrically conductive chip carrier. Each LED has a second electrical terminal electrically coupled to the connection pad of a corresponding one of the first, second, and third electrically conductive connection parts.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Cased electrical component

The invention relates to a cased electrical component comprising a carrier substrate ( 10 ), a spring device ( 20 ), which is arranged on the carrier substrate ( 10 ), a chip ( 30 ), which on a first side ( 31 ) of the chip is coupled to the spring device ( 20 ), and a cover element ( 100 ), which is arranged on the carrier substrate ( 10 ). The cover element ( 100 ) is arranged over the chip ( 20 ) such that the cover element ( 100 ) is in contact with the chip ( 30 ) at least on a second side ( 32 ) of the chip, which is different from the first side. The component has a low space requirement and is highly sealed with respect to influences from the surroundings.

Fluid storage and dispensing system including dynamic fluid monitoring of fluid storage and dispensing vessel

A monitoring system for monitoring fluid in a fluid supply vessel during operation including dispensing of fluid from the fluid supply vessel. The monitoring system includes (i) one or more sensors for monitoring a characteristic of the fluid supply vessel or the fluid dispensed therefrom, (ii) a data acquisition module operatively coupled to the one or more sensors to receive monitoring data therefrom and responsively generate an output correlative to the characteristic monitored by the one or more sensors, and (iii) a processor and display operatively coupled with the data acquisition module and arranged to process the output from the data acquisition module and responsively output a graphical representation of fluid in the fluid supply vessel, billing documents, usage reports, and/or resupply requests.

Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure

A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

Devices and methods

A device comprising an arrangement of device materials and a layer comprising a material with heat-dissipating properties disposed over at least a portion thereof is disclosed. The device can further include an interleave layer disposed between the top surface of the arrangement of device materials and the layer comprising a material with heat-dissipating properties. A barrier layer may further be included between the arrangement of device materials and the layer comprising a material with heat-dissipating properties. Methods are also disclosed. In certain embodiments, a device includes quantum confined semiconductor nanoparticles.

Multi-Chip Module and Method of Manufacture

A multi-chip module and a method for manufacturing the multi-chip module that mitigates wire breakage. A first semiconductor chip is mounted and wirebonded to a support substrate. A spacer is coupled to the first semiconductor chip. A support material is disposed on the spacer and a second semiconductor chip is positioned on the support material. The second semiconductor chip is pressed into the support material squeezing it into a region adjacent the spacer and between the first and second semiconductor chips. Alternatively, the support material is disposed on the first semiconductor chip and a die attach material is disposed on the spacer. The second semiconductor chip is pressed into the die attach material and the support material, squeezing a portion of the support material over the spacer edges. Wirebonds are formed between the support substrate and the first and second semiconductor chips.

Compliant printed circuit semiconductor package

A method of making a package for a semiconductor device having electrical terminals. At least one semiconductor device is located on a substrate. A first dielectric layer is printed on at least a portion of the semiconductor device to include first recesses aligned with a plurality of the electrical terminals. A conductive material is deposited in the first recesses forming contact members. A second dielectric layer is printed on at least a portion of the first dielectric layer to include second recesses aligned with a plurality of the first recesses. A conductive material is deposited in at least a portion of the second recesses to include a circuit geometry and a plurality of exposed terminals. A compliant material is deposited in recesses in one or more of the first and second dielectric layers adjacent to a plurality of the exposed terminals.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

Method of Joining Metal-Ceramic Substrates to Metal Bodies

A method of joining a metal-ceramic substrate having metalization on at least one side to a metal body by using a metal alloy is disclosed. The metal body has a thickness of less than 1.0 mm, and the metal alloy contains aluminum and has a liquidus temperature of greater than 450° C. The resulting metal-ceramic module provides a strong bond between the metal body and the ceramic substrate. The resulting module is useful as a circuit carrier in electronic appliances, with the metal body preferably functioning as a cooling body. 112-. (canceled)13. A module comprising:a metal-ceramic substrate having metalization on at least one side, wherein the metal-ceramic substrate is adapted to have a semiconductor component disposed on at least one metalized side of the metal-ceramic substrate, and wherein the metal-ceramic substrate includes a ceramic substrate and no more than two metal layers each of which directly contacts the ceramic substrate;a metal body having a thickness of less than 1 mm; anda joining region joining the ceramic substrate to the metal body, the joining region including a metal alloy containing aluminum and having a liquidus temperature of greater than 450° C.14. The module of claim 13 , wherein the peeling force required for separating the metal-ceramic substrate from the metal body is greater than 3 N/mm.15. The module of used as a circuit carrier in an electronic appliance.16. The module of claim 13 , wherein a surface of the metal-ceramic substrate that contacts the metal alloy has a first surface area claim 13 , wherein a surface of the metal body that contacts the metal alloy has a second surface area claim 13 , and wherein the first surface area is smaller than the second surface area.17. The module of claim 13 , wherein the metal alloy further comprises silicon.18. The module of claim 13 , wherein the metal alloy further comprises magnesium.19. The module of claim 13 , wherein based on the total weight of the metal alloy claim 13 , the metal ...

METHIOD OF MANUFACTURING AN IMPLANTABLE ELECTRODE ARRAY BY FORMING PACKAGES AROUND THE ARRAY CONTROL MODULES AFTER THE CONTROL MODULES ARE BONDED TO SUBSTRATES

A method of forming an implantable electrode array that includes one or more packaged control modules. A control module is packaged by mounting the module to a substrate and forming a containment ring around the module. A conformal coating is disposed over the surface of the module to cover the carrier. Within the containment ring, the conformal coating hardens to form a non-porous shell around the control module. The one or more packaged control modules are placed in a flexible array. Electrodes that are mounted to or embedded in the flexible carrier are connected to the one or more control modules. 1. A method of assembling an implantable electrode array , said method including the steps of: forming a containment ring on a first surface of a substrate;', 'mounting a control module to the first surface of the substrate so that the control module is disposed in the containment ring;', 'applying a coating to the first surface of the substrate so that the coating is disposed in the containment ring around the control module so that the coating forms a non-porous shell in the containment ring around the control module;', 'bonding a lid over the containment ring so that the lid extends over the control module and the shell so as to form at least one packaged control module, 'packaging at least one control module according to the steps ofembedding the at least one packaged control module in a flexible carrier; andelectrically connecting the at least one packaged control module to at least one electrode that is disposed over or embedded in the flexible carrier.2. The method of assembling an implantable electrode array of claim 1 , wherein: said step of forming a containment ring of the first surface of the substrate is performed by forming the containment ring so that the containment ring is at least partially located inwardly of an outer perimeter of the containment ring;', 'in said step of applying a coating to the first surface of the substrate, the coating is applied ...

Illumination apparatus

An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array. 1. A method for providing an illumination apparatus , comprising:selectively removing a plurality of light-emitting elements from a monolithic array of light-emitting elements in a manner that preserves the relative spatial position of the selectively removed light-emitting elements;forming a non-monolithic array of light-emitting elements with the removed plurality of light-emitting elements in a manner that preserves the relative spatial position of the selectively removed light-emitting elements;determining a group of light-emitting elements of the non-monolithic array which fails at least one functional criterion; andchanging an electrical drive to at least one light-emitting element of the non-monolithic array such that the group of light-emitting elements which failed the at least one functional criterion passes the at least one functional criterion following the change.2. The method according to claim 1 , wherein the plurality of light-emitting elements that are selectively removed from the monolithic array are selected such that claim 1 , in at least one direction claim 1 , for at least one pair of the selectively removed light-emitting elements in the at least one direction claim 1 , for each respective pair there is at least one respective light-emitting element that is not selected that was positioned in the monolithic array between the pair of removed light-emitting elements in the at least one direction.3. The method according to claim 1 , wherein changing the electrical drive comprises creating or removing a short ...

Apparatus with Light Emitting or Absorbing Diodes

An exemplary printable composition of a liquid or gel suspension of diodes generally includes a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary apparatus may include: a plurality of diodes; at least a trace amount of a first solvent; and a polymeric or resin film at least partially surrounding each diode of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASED POST HEIGHT

An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces. 1. An interconnection substrate , comprising:a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions;electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, the conductive projections extending from the conductive elements above the at least one wiring layer, the conductive projections having end portions remote from the conductive elements and neck portions between the conductive elements and the end portions, the end portions having lower surfaces extending outwardly from the neck portions in at least one of the lateral directions; anda dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces, at least portions of the dielectric layer between the conductive projections being recessed below a height of the lower surfaces.2. The substrate of claim 1 , wherein the dielectric layer is a solder mask.3. The substrate of claim 1 , ...

Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure

A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

Integrated Circuit Package Including Miniature Antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115°, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna. 1. A wireless system comprising:a substrate;a chip mounted on the substrate;a sensor mounted on the substrate;a first antenna mounted on the substrate and enclosed in a first rectangular area that does not enclose the chip, the first antenna comprising a first conducting pattern having a perimeter, wherein the perimeter of the first conducting pattern defines a first curve comprising at least five segments, wherein: each of the at least five segments forms an angle with each adjacent segment, at least three of the segments are smaller than a tenth of a longest free-space operating wavelength of the first antenna, each angle between adjacent segments is less than 180°, and at least two of the angles between adjacent segments are less than 115°; anda second antenna mounted on the substrate and enclosed in a second rectangular area having a longer side shorter than one-fifth of a longest free-space operating ...

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface. 1. A method comprising:constraining a portion of multiple chips adjacent a hardened material such that the hardened material and the multiple chips behave as a rigid body;transferring a force from the hardened material on the rigid body to the multiple chips to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element, without causing damage to the multiple chips or the bonding surface of the element; andremoving the hardened material from contact with the multiple chips.2. The method of claim 1 , further comprising moving the multiple chips constrained by the hardened material from a first location to a second location.3. The method of claim 1 , further comprising bonding each of the multiple chips to the element.4. The method of claim 1 , further comprising removing the rigid body using at least one of a chemical process claim 1 , a mechanical process claim 1 , or a chemical-mechanical process.5. The method of claim 1 , further comprising removing at least a portion of the hardened material through at least one of a chemical process claim 1 , a mechanical process claim 1 ...

Fan-Out WLP With Package

The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and electrically connecting redistribution contacts on the microelectronic unit and terminals on the substrate with a conductive matrix material extending within at least one opening extending through the substrate.

Micro-reflectors on a substrate for high-density led array

The present invention provides an optical array module that includes a plurality of semiconductor devices mounted on a thermal substrate formed with a plurality of openings that function as micro-reflectors, wherein each micro-reflector includes a layer of reflective material to reflect light. Such material preferably is conductive so as to provide electrical connection for its associated semiconductor device.

CASED ELECTRICAL COMPONENT

The invention relates to a cased electrical component comprising a carrier substrate (), a spring device (), which is arranged on the carrier substrate (), a chip (), which on a first side () of the chip is coupled to the spring device (), and a cover element (), which is arranged on the carrier substrate (). The cover element () is arranged over the chip () such that the cover element () is in contact with the chip () at least on a second side () of the chip, which is different from the first side. The component has a low space requirement and is highly sealed with respect to influences from the surroundings. 1. A method for producing a cased electrical component , comprising:providing a carrier substrate;arranging a spring device on the carrier substrate;arranging a chip on the spring device in such a way that a first side of the chip is coupled to the spring device; andarranging a covering element over the chip in such a way that the covering element touches the chip at least at a second side of the chip, the second side being different from the first side.2. The method according to claim 1 , wherein arranging the spring device on the carrier substrate comprises:sputtering and electrodepositing a first layer on the carrier substrate;sputtering and electrodepositing a second layer on an end section of the first layer and on a photoresist; andremoving the photoresist below the second layer.3. The method according to claim 2 , further comprising arranging a bearing element on the carrier substrate by:sputtering and electrodepositing a third layer on the carrier substrate; andmechanically post-processing the third layer in such a way that the third layer has a planar surface suitable for bearing for the chip.4. The method according to claim 3 , further comprising arranging the covering element on the carrier substrate by:laminating a film composed of a material composed of plastic over the chip and the carrier substrate; andsputtering and electrodepositing a fourth ...

Diode for a Printable Composition

An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary diode comprises: a light emitting or absorbing region having a diameter between about 20 and 30 microns and a height between about 2.5 to 7 microns; a first terminal coupled to the light emitting region on a first side, the first terminal having a height between about 1 to 6 microns; and a second terminal coupled to the light emitting region on a second side opposite the first side, the second terminal having a height between about 1 to 6 microns.

Semiconductor device and production method therefor

An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE INCLUDING METAL PATTERNS AND CUT-OUT SECTION

A light emitting device includes a substrate; a light emitting element mounted on an upper surface of the substrate; a light-reflecting member surrounding lateral surfaces of the light emitting element; and a sealing member disposed over an upper surface of the light emitting element and an upper surface of the light-reflecting member. An outer edge of the upper surface of the light-reflecting member coincides with an outer edge of a lower surface of the sealing member. 1. A light emitting device comprising:a substrate;a light emitting element mounted on an upper surface of the substrate;a light-reflecting member surrounding lateral surfaces of the light emitting element; anda sealing member disposed over an upper surface of the light emitting element and an upper surface of the light-reflecting member,wherein an outer edge of the upper surface of the light-reflecting member coincides with an outer edge of a lower surface of the sealing member.2. The light emitting device according to claim 1 ,wherein an inner edge of the upper surface of the light-reflecting member is located higher than the outer edge in the height direction, andwherein the upper surface of the light-reflecting member is a concave curved surface.3. The light emitting device according to claim 1 , wherein the substrate comprises a first metal part and a second metal part at the upper surface of the substrate.4. The light emitting device according to claim 3 , wherein claim 3 , in a plan view claim 3 , the second metal part is located at a center of the substrate and is sandwiched by two portions of the first metal part.5. The light emitting device according to claim 3 ,wherein the light emitting element comprises a first electrode and a second electrode on a same surface, andwherein the light emitting element is mounted on the substrate upper surface such that the first electrode of the light emitting element faces the first metal part of the substrate, and the second electrode of the light ...

Method of manufacturing light emitting device including metal patterns and cut-out section

A light emitting device includes a support member having a mounting surface. The support member includes an insulating member having top surface and a plurality of side surfaces, a first metal pattern disposed on the top surface of the insulating member, and a second metal pattern disposed on the side surface of the insulating member such that a side surface of the second metal pattern is continuous with a top surface of the first metal pattern. The light emitting device further includes a light emitting element mounted on the mounting surface at a location of the first metal pattern, and a bonding member that bonds the light emitting element to the mounting surface. The bonding member covers at least a portion of the first metal pattern and at least a portion of the second metal pattern.

Three-dimensional structure in which wiring is provided on its surface

One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Illumination apparatus

An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.

Hybrid combination of substrate and carrier mounted light emitting devices

A multi-chip light emitting device (LED) uses a low-cost carrier structure that facilitates the use of substrates that are optimized to support the devices that require a substrate. Depending upon the type of LED elements used, some of the LED elements may be mounted on the carrier structure, rather than on the more expensive ceramic substrate. In like manner, other devices, such as sensors and control elements, may be mounted on the carrier structure as well. Because the carrier and substrate structures are formed independent of the encapsulation and other after-formation processes, these structures can be tested prior to encapsulation, thereby avoiding the cost of these processes being applied to inoperative structures.

Integrated Circuit Structures, Semiconductor Structures, And Semiconductor Die

Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.

Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core

A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Integrated antenna for rfic package applications

A chip package includes a set of layers including conductive planes connected by vias. A first portion has at least one antenna, antenna ground plane, and first grounded vias. A second portion has a conductive plane parallel to the ground plane that forms an interface for connecting to at least one integrated circuit device. A third portion between the first and the second portion has a vertical transmission line that includes a signal via connecting the antenna feed line to the at least one integrated circuit and a parallel-plate mode suppression mechanism. The parallel-plate mode suppression mechanism includes a grounded reflector that forms a cage with the grounded vias around an antenna region and further includes second ground vias surrounding the signal via.

LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE

A light emitting device () includes a base member (), electrically conductive members () disposed on the base member (), a light emitting element () mounted on the electrically conductive members (), an insulating filler () covering at least a portion of surfaces of the electrically conductive members () where the light emitting element () is not mounted, and a light transmissive member () covering the light emitting element (). 1. A light emitting device comprising:a light emitting element having a semiconductor layer and a transparent substrate;a reflective member exposing at least apart of side surfaces and a top surface of the transparent substrate and covering side surfaces of the semiconductor layer; anda light transmissive member covering a portion of the transparent substrate exposed from the reflective member.2. The light emitting device according to further comprising a base member and electrically conductive members disposed on the base member claim 1 , wherein the light emitting element is mounted on the electrically conductive members claim 1 , at a surface of the electrically conductive members claim 1 , at least a portion of which does not have the light emitting element mounted thereon is covered with an insulating filler which is the reflective member claim 1 , and the light transmissive member covers the light emitting element.3. The light emitting device according to claim 2 , wherein the base member has a recess and the electrically conductive members are disposed on a bottom surface and side surfaces of the recess claim 2 , and the light emitting element is mounted on the bottom surface of the recess.4. The light emitting device according to claim 3 , wherein the side surfaces of the recess has claim 3 , at a portion abutting on a top edge surface of the recess have a region where an electrically conductive member is not formed.5. The light emitting device according to claim 3 , wherein the side surfaces of the recess at a portion abutting on ...

SEMICONDUCTOR PACKAGE INCLUDING ORGANIC INTERPOSER

A semiconductor package including an organic interposer includes: the organic interposer including insulating layers and wiring layers formed on the insulating layers; a stiffener disposed on the interposer and having a through-hole; a first semiconductor chip disposed in the organic through-hole on the organic interposer; a second semiconductor chips disposed adjacent to the first semiconductor chip in the through-hole on the organic interposer; and an underfill resin filling at least portions of the through-hole and fixing the first semiconductor chip and the second semiconductor chip, wherein the connection pads of the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the wiring layers of the organic interposer. 1. A semiconductor package , comprising:an organic interposer including insulating layers and wiring layers formed on the insulating layers;a stiffener disposed on the organic interposer and having a through-hole;a first semiconductor chip disposed in the through-hole on the organic interposer and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;a second semiconductor chip disposed adjacent to the first semiconductor chip in the through-hole on the organic interposer, the second semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surfaces; andan underfill resin filling at least portions of the through-hole and fixing the first semiconductor chip and the second semiconductor chip,wherein the connection pads of the first semiconductor chip and the plurality of second semiconductor chips are electrically connected to each other through the wiring layers of the organic interposer.2. The semiconductor package of claim 1 , wherein the second semiconductor chip comprises a plurality of second semiconductor chips claim 1 , and wherein at least portions of the ...

White light devices using non-polar or semipolar gallium containing materials and phosphors

A packaged optical device includes a substrate having a surface region with light emitting diode devices fabricated on a semipolar or nonpolar GaN substrate. The light emitting diodes emit polarized light and are characterized by an overlapped electron wave function and a hole wave function. Phosphors within the package are excited by the polarized light and, in response, emit electromagnetic radiation of a second wavelength.

High Density Three-dimensional Integrated Capacitors

A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates. 1. A component having electrodes for electrical interconnection with a circuit component or microelectronic element , comprising:a substrate consisting essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C., the substrate having a first surface, a second surface opposite the first surface, and an opening in the first surface having at least one dimension greater than 5 microns in a direction along the first surface, the opening extending downwardly from the first surface; and first and second electrically conductive plates connectable with respective first and second electric potentials, the first and second plates extending along an inner surface of the opening, the first and second plates being separated from one another by a dielectric layer, the first plate being grounded to the substrate; and', 'first and second electrodes, the first electrode exposed at the first surface and electrically connected to the first plate, the second electrode exposed at one of the first and second surfaces and electrically connected to the second plate., 'a capacitor, including2. A component having electrodes ...

Light emitting device and method for manufacturing the same

By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same.

Electronic device

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Compact Media Player

An electronic device such as a media player may be formed from electrical components such as integrated circuits, buttons, and a battery. Electrical input-output port contacts may be used to play audio and to convey digital signals. Electrical components for the device may be mounted to a substrate. The components may be encapsulated in an encapsulant and covered with an optional housing structure. The electrical input-output port contacts and portions of components such as buttons may remain uncovered by encapsulant during the encapsulation process. Integrated circuits may be entirely encapsulated with encapsulant. The integrated circuits may be packaged or unpackaged integrated circuit die. The substrate may be a printed circuit board or may be an integrated circuit to which components are directly connected without interposed printed circuit board materials.

Light emitting device and method for manufacturing the same

By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same.

Optoelectronic system

An embodiment of the invention discloses an optoelectronics system. The optoelectronic system includes an optoelectronic element having a first width; an adhesive material enclosing the optoelectronic element and having a second width larger than the first width; a phosphor structure formed between the optoelectronic element and the adhesive material; and a transparent substrate formed on the adhesive material.

SEMICONDUCTOR PACKAGE INCLUDING ORGANIC INTERPOSER

A semiconductor package including an organic interposer includes: the organic interposer including insulating layers and wiring layers formed on the insulating layers; a stiffener disposed on the interposer and having a through-hole; a first semiconductor chip disposed in the organic through-hole on the organic interposer; a second semiconductor chips disposed adjacent to the first semiconductor chip in the through-hole on the organic interposer; and an underfill resin filling at least portions of the through-hole and fixing the first semiconductor chip and the second semiconductor chip, wherein the connection pads of the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the wiring layers of the organic interposer. 118-. (canceled)19. A semiconductor package , comprising:an organic interposer including wiring layers;a first semiconductor chip disposed on the organic interposer and electrically connected to the wiring layers of the organic interposer;a plurality of second semiconductor chips disposed adjacent to the first semiconductor chip and electrically connected to the wiring layers of the organic interposer, wherein two or more plurality of second semiconductor chips among the plurality of second semiconductor chips are adjacent to one side of the first semiconductor chip and two or more plurality of second semiconductor chips among the plurality of second semiconductor chips are adjacent to the other side opposite to the one side of the first semiconductor chip;a warpage control material disposed on the organic interposer and having a surrounding portion surrounding the first semiconductor chip and the plurality of second semiconductor chips, and a plurality of protruding portions extending from the surrounding portion to between two adjacent second semiconductor chips adjacent to the same side of the first semiconductor chip among the plurality of second semiconductor chips; andan underfill resin ...

Semiconductor device

The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101 , an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113 , and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101 . The interconnect component 101 has a constitution where an interconnect layer 103 , a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Electrical Feedthrough Assembly

A device includes a hermetically sealed case with electronic circuitry housed within. One surface of the hermetically sealed case includes a metallic plate and a co-fired ceramic electrical feedthrough with a number of vias. The co-fired ceramic electrical feedthrough is hermetically joined to the metallic plate and a hybrid circuit is connected to the feedthrough. 1. A feedthrough comprising:a body having a first side and a second side separated by a thickness;a first conductive pad on the first side;a second conductive pad on the second side; anda plurality of conductive vias electrically connecting the first conductive pad and the second conductive pad.2. The feedthrough of claim 1 , wherein the first conductive pad and second conductive pad comprise different materials.3. The feedthrough of claim 1 , wherein the first conductive pad and the second conductive pad have a common geometry.4. The feed through of claim 3 , wherein a center point of the first conductive pad and a center point of the second conductive pad could be connected by a straight line perpendicular to the first and second conductive pads.5. The feedthrough of claim 1 , wherein the vias have a common geometry.6. The feedthrough of claim 1 , wherein the vias are equidistant from each other.7. The feedthrough of claim 1 , wherein a center of a cross-section of each via is equidistant from a center-point of the first conductive pad.8. The feedthrough of claim 1 , wherein the plurality of vias comprises three vias.9. The feedthrough of claim 1 , wherein each via has a separate contact with the first conductive pad.10. The feedthrough of claim 1 , wherein each via does not electrically communicate with any other via except through the first and second conductive pads.11. The feedthrough of claim 1 , wherein a projection of each via onto the first side remains within a perimeter of the first conductive pad.12. The feedthrough of claim 1 , wherein each via is straight and extends perpendicular to the ...

HIGH-FREQUENCY MODULE

A high-frequency module la includes: a wiring substrate a plurality of components and that are mounted on an upper surface of the wiring substrate a sealing resin layer that is stacked on the upper surface of the wiring substrate a shield film that covers a surface of the sealing resin layer and a shield wall that is provided in the sealing resin layer The shield wall is formed of two shield wall element bodies and that have straight line shapes in a plan view, and the two shield wall element bodies and are arranged such that the shield wall element bodies each have one end surface that is not exposed at a different peripheral side surface of the sealing resin layer 1. A high-frequency module comprising:a wiring substrate;a plurality of components mounted on a main surface of the wiring substrate;a sealing resin layer stacked on the main surface of the wiring substrate and sealing the plurality of components; anda shield wall provided in the sealing resin layer and arranged so as to partition the sealing resin layer into a plurality of regions, wherein at least one prescribed component is respectively mounted in each of the plurality of regions;wherein the shield wall includes a plurality of shield wall element bodies, and each of the plurality of shield wall element bodies has at least one end portion not exposed at a side surface of the sealing resin layer.2. The frequency module according to claim 1 , wherein the shield wall partitions the sealing resin layer into two regions claim 1 , and wherein when one of the two regions partitioned by the shield wall is viewed from another one of the two regions claim 1 , at least a part of one of the plurality of shield wall element bodies different from another one of the plurality of shield wall element bodies is arranged in a place where the other shield wall element body is not arranged.3. The frequency module according to claim 2 ,wherein the plurality of shield wall element bodies are each arranged so as to be ...

PACKAGED SEMICONDUCTOR COMPONENTS HAVING SUBSTANTIALLY RIGID SUPPORT MEMBERS AND METHODS OF PACKAGING SEMICONDUCTOR COMPONENTS

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die. 1. A packaged semiconductor component , comprising:a semiconductor die having a first composition, a first surface, a bond pad located on or near the first surface, and a second surface opposite the first surface;an array of photo sensors at least partially embedded in the semiconductor die proximate to the first surface;a support member attached to the first surface of the semiconductor die, the support member being at least substantially rigid and having a second composition different from the first composition of the semiconductor die, the support member including an opening generally aligned with the bond pad located on or near the first surface;a substrate carrying the semiconductor die and the support member attached to the semiconductor die; andan encapsulant at least partially encasing the semiconductor die, the support member, and the substrate.2. The packaged semiconductor component of claim 1 , wherein the package further includes a plurality of solder balls between the first surface of the semiconductor die and the substrate claim 1 , individual solder balls electrically connecting the bond pad of the semiconductor die to the substrate.3. The packaged semiconductor component of wherein the semiconductor die is a first semiconductor die and the package further includes a second semiconductor die claim 1 , and wherein the support member is between the first and second semiconductor dies.4. The packaged semiconductor ...

Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation

A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

Compact Media Player

An electronic device such as a media player is formed from electrical components such as integrated circuits, buttons, and a battery. Electrical input-output port contacts are used to play audio and to convey digital signals. Electrical components for the device are mounted to a substrate. The components are encapsulated in an encapsulant and covered with an optional housing structure. The electrical input-output port contacts and portions of components such as buttons remain uncovered by encapsulant during the encapsulation process. Integrated circuits are entirely encapsulated with encapsulant. The integrated circuits are packaged or unpackaged integrated circuit die. The substrate is a printed circuit board or is an integrated circuit to which components are directly connected without any printed circuit boards interposed between the integrated circuit and the components. 1. A portable electronic device , comprising:a substrate;an integrated circuit mounted on the substrate, wherein the integrated circuit includes an audio circuit that produces audio signals;a battery; andencapsulant that encapsulates the integrated circuit, the substrate, and the battery, wherein the encapsulant forms an external surface of the portable electronic device.3. The portable electronic device defined in claim 1 , wherein the substrate is a printed circuit board.3. The portable electronic device defined in claim 1 , wherein the battery is mounted on the substrate.4. The portable electronic device defined in claim 1 , further comprising a user-input component mounted on the substrate.5. The portable electronic device defined in claim 4 , wherein the user-input component is a button.6. The portable electronic device defined in claim 4 , wherein the user-input component is a touch-sensitive component.7. The portable electronic device defined in claim 1 , further comprising input-output port contacts formed on the substrate.8. The portable electronic device defined in claim 1 , further ...

MILLIMETER WAVE LTCC FILTER

The present disclosure provides a millimeter wave LTCC filter including system ground layers and metalized vias; two first perturbation metallized vias provided in a first substrate integrated waveguide unit and two second perturbation metallized vias provided in a second substrate integrated waveguide unit; the two first perturbation metallized vias are symmetrically provided on a first diagonal of the first closed resonant cavity with respect to a geometric center of the first closed resonant cavity; the two second perturbation metallized vias are symmetrically provided on a second diagonal of the second closed resonant cavity with respect to a geometric center of the second closed resonant cavity, and the first diagonal and the second diagonal are orthogonal to each other; a first port and a second port. Compared with the related art, the millimeter wave LTCC filter of the present disclosure is small in volume, large in bandwidth, and low in loss. 1. A millimeter wave LTCC filter , comprising:system ground layers, comprising a first system ground layer, a second system ground layer, and a third system ground layer that are sequentially stacked from top to bottom at intervals, wherein two adjacent layers of the system ground layers define one closed resonant cavity; three layers of the system ground layers sequentially define, from top to bottom, a first closed resonant cavity and a second closed resonant cavity that have same peripheral dimensions and communicate with each other; and each of the first closed resonant cavity and the second closed resonant cavity is of a rectangular structure;metallized vias, comprising, in a direction in which the system ground layers are stacked, a plurality of first metallized vias penetrating the first closed resonant cavity, and a plurality of second metallized vias penetrating the second closed resonant cavity, wherein the plurality of first metallized vias is equally spaced along a circumference of the first closed resonant ...

CERAMIC COMPOSITE AND PRODUCTION METHOD FOR CERAMIC COMPOSITE

To provide a ceramic composite and a production method therefor allowing ease of processing to be improved and fracture toughness to be improved simultaneously. The invention includes the steps of: preparing at least a liquid-form resin and a ceramic sintered body which has been sintered at a temperature which is 700° C. to 100° C. less than a sintering temperature at which a theoretical density is obtained; immersing the ceramic sintered body in the liquid-form resin, causing the liquid-form resin to infiltrate the ceramic sintered body; and hardening the infiltrated liquid-form resin to obtain a ceramic composite having a relative density of between 40% and 90% by causing the resin to infiltrate. Gaps where no resin has infiltrated are formed in the ceramic composite. 1. A ceramic composite in which a resin is infiltrated into a ceramic sintered body to have a relative density of 40% or more and 90% or less.2. The ceramic composite according to claim 1 , wherein the relative density is 45% or more and 60% or less.3. The ceramic composite according to claim 1 , wherein gaps where the resin is not infiltrated are formed.4. The ceramic composite according to claim 1 , wherein a thickness of the thinnest part is 0.04 mm or more and 0.06 mm or less.5. The ceramic composite according to claim 1 , wherein fracture toughness is more than 0.11 MPamand less than 0.21 MPam.6. The ceramic composite according to claim 1 , wherein the resin is either polyvinyl alcohol or a polymethyl methacrylate resin.7. The ceramic composite according to claim 1 , wherein a ceramic material forming the ceramic sintered body is any one of silica claim 1 , alumina claim 1 , zirconia claim 1 , hydroxyapatite claim 1 , and β-tricalcium phosphate.8. A production method for a ceramic composite comprising: preparing at least a ceramic sintered body and a liquid resin claim 1 , the ceramic sintered body obtained by being sintered at a temperature −700° C. or more and −100° C. or less lower than a ...

High Density Three-dimensional Integrated Capacitors

A component includes a substrate and electrically conductive layers formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The electrically conductive layers can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates. 1. A microelectronic element , comprising:a substrate having a coefficient of thermal expansion of less than 10 ppm/° C., the substrate having a first surface, a second surface opposite the first surface, and an opening extending downwardly from the first surface; andfirst and second electrically conductive layers connectable with respective first and second electric potentials, the first and second layers extending along an inner surface of the opening, the first and second layers being separated from one another by a first dielectric layer; andfirst and second electrodes, the first electrode at the first surface and electrically connected to the first layer, the second electrode at one of the first and second surfaces and electrically connected to the second layer,wherein the first and second electrodes are connected to the first and second layers at respective first and second locations, the second electrode being at the first surface, the first and second locations are at least 5 microns apart horizontally along the first surface.2. The component as claimed in claim 1 , wherein the first ...

Methods of forming 3-d circuits with integrated passive devices

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.