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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 7469. Отображено 100.

02-02-2012 дата публикации

Surface mounted led structure and packaging method of integrating functional circuits on a silicon

Номер: US20120025242A1

Автор: Guowei David Xiao, Haiying Chen, YU Hou, Yugang Zhou, Zhaoming Zeng

Принадлежит: Apt Electronics Co ltd

The present invention relates to a surface mounted LED structure of integrating functional circuits on a silicon substrate, comprising the silicon substrate and an LED chip. Said silicon substrate has an upper surface of planar structure without grooves. An oxide layer covers the upper surface of the silicon substrate, and metal electrode layers are arranged in the upper surface of the oxide layer. The upper surfaces of said metal electrode layers are arranged with metal bumps, and the LED chip is flip-chip mounted to the silicon substrate. Two conductive metal pads are arranged on the lower surface of said silicon substrate, said conductive metal pads are electrically connected to the metal electrode layers on the upper surface of the silicon substrate by a metal lead arranged on the side wall of the silicon substrate. A heat conduction metal pad is arranged on the corresponding lower, surface of the silicon substrate just below the LED chip. Peripheral functional circuits required by LED are integrated on the upper surface of said silicon substrate. The structure of the present invention has advantages of good heat dissipation effect and small volume, and direct integration of functional circuits such as protection and drive circuits etc. in the silicon substrate achieves large-scale production package of wafer level, reducing the cost of packaging and lighting fixture.

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Номер записи: 1

09-02-2012 дата публикации

Gain Enhanced LTCC System-on-Package for UMRR Applications

Номер: US20120032836A1

Автор: Atif SHAMIM, Farhan Abdul Ghaffar, Khaled Nabil Salama, Muhammad Umair Khalid

Принадлежит: King Abdullah University of Science and Technology KAUST

An apparatus, system, and method for Gain Enhanced LTCC System-on-Package radar sensor. The sensor includes a substrate and an integrated circuit coupled to the substrate, where the integrated circuit is configured to transmit and receive radio frequency (RF) signals. An antenna may be coupled to the integrated circuit and a lens may be coupled to the antenna. The lens may be configured to enhance the gain of the sensor.

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Номер записи: 2

16-02-2012 дата публикации

Thermal expansion suppressing member and anti-thermally-expansive member

Номер: US20120040196A1

Автор: Hisato Yabuta, Kaoru Miura, Makoto Kubota, Masaki Azuma, Yoshihiko Matsumura, Yuichi Shimakawa

Принадлежит: Canon Inc, KYOTO UNIVERSITY

Provided are a thermal expansion suppressing member having negative thermal expansion properties and a metal-based anti-thermally-expansive member having small thermal expansion. More specifically, provided are a thermal expansion suppressing member, including at least an oxide represented by the following general formula (1), and an anti-thermally-expansive member, including a metal having a positive linear expansion coefficient at 20° C., and a solid body including at least an oxide represented by the following general formula (1), the metal and solid being joined to each other: (Bi 1-x M x )NiO 3 (1) where M represents at least one metal selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y, and In; and x represents a numerical value of 0.02≦x≦0.15.

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Номер записи: 3

23-02-2012 дата публикации

Image Sensor Package with Dual Substrates and the Method of the Same

Номер: US20120043635A1

Автор: Wen-Kun Yang

Принадлежит: King Dragon International Inc

The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.

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Номер записи: 4

22-03-2012 дата публикации

Inductive getter activation for high vacuum packaging

Номер: US20120068300A1

Автор: Jeffery F. Summers

Принадлежит: Innovative Micro Technology

An approach to activating a getter within a sealed vacuum cavity is disclosed. The approach uses inductive coupling from an external coil to a magnetically permeable material deposited in the vacuum cavity. The getter material is formed over this magnetically permeable material, and heated specifically thereby, leaving the rest of the device cavity and microdevice relatively cool. Using this inductive coupling technique, the getter material can be activated after encapsulation, and delicate structures and low temperature wafer bonding mechanisms may be used.

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Номер записи: 5

29-03-2012 дата публикации

Methods of fabricating package stack structure and method of mounting package stack structure on system board

Номер: US20120074586A1

Автор: Eun-Jin Choi, Sun-Kyoung SEO

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

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Номер записи: 6

12-04-2012 дата публикации

Chip stacked structure

Номер: US20120086119A1

Автор: Ming-Che Wu

Принадлежит: Universal Global Scientific Industrial Co Ltd, Universal Scientific Industrial Shanghai Co Ltd

A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

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Номер записи: 7

12-04-2012 дата публикации

Semiconductor assembly and semiconductor package including a solder channel

Номер: US20120086123A1

Автор: Jeong-Woo Park, Moon-Gi Cho, Sun-Hee Park, Ui-Hyoung Lee

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

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Номер записи: 8

12-04-2012 дата публикации

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

Номер: US20120088338A1

Автор: Alan P. Boone, Nathan P. Lower, Ross K. Wilcoxon

Принадлежит: ROCKWELL COLLINS INC

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

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Номер записи: 9

26-04-2012 дата публикации

Thermosetting resin composition for sealing packing of semiconductor, and semiconductor device

Номер: US20120101191A1

Автор: Akira Nagai, Emi Miyazawa, Kazutaka Honda, Keisuke Ookubo, Tetsuya Enomoto

Принадлежит: Hitachi Chemical Co Ltd

A thermosetting resin composition for an underfilling of a semiconductor comprising, as essential components, a thermosetting resin, a curing agent, a flux agent and two or more inorganic fillers with different mean particle sizes, wherein the inorganic fillers include an inorganic filler with a mean particle size of no greater than 100 nm and an inorganic filler with a mean particle size of greater than 100 nm.

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Номер записи: 10

03-05-2012 дата публикации

Through wiring substrate and manufacturing method thereof

Номер: US20120103679A1

Автор: Hirokazu Hashimoto, Satoshi Yamamoto

Принадлежит: Fujikura Ltd

A through wiring substrate includes a substrate having a first face and a second face; and a through-wire formed by filling, or forming a film of, an electrically-conductive substance into a through-hole, which penetrates between the first face and the second face. The through-hole has a bend part comprising an inner peripheral part that is curved in a recessed shape and an outer peripheral part that is curved in a protruding shape, in a longitudinal cross-section of the through-hole, and at least the inner peripheral part is formed in a circular arc shape in the longitudinal cross-section.

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Номер записи: 11

03-05-2012 дата публикации

Thermal Power Plane for Integrated Circuits

Номер: US20120105145A1

Автор: Andreas Huber, Bruno Michel, Harry Barowski, Hubert Harrer, Jochen Supper, Stephan Paredes, Thomas Brunschwiler, Tim Niggemeier

Принадлежит: International Business Machines Corp

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

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Номер записи: 12

10-05-2012 дата публикации

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

Номер: US20120112327A1

Автор: Reza A. Pagaila, Yaojian Lin

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

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Номер записи: 13

10-05-2012 дата публикации

Ceramic/metal composite structure and method of manufacturing the same

Номер: US20120114966A1

Автор: Shao-Kuan Lee, Wei-Hsing Tuan

Принадлежит: National Taiwan University NTU

A ceramic/metal composite structure includes an aluminum oxide substrate, an interface bonding layer and a copper sheet. The interface bonding layer is disposed on the aluminum oxide substrate. The copper sheet is disposed on the interface bonding layer. The interface bonding layer bonds the aluminum oxide substrate to the copper sheet. Some pores are formed near or in the interface bonding layer. A porosity of the interface bonding layer is substantially smaller than or equal to 25%. A method of manufacturing the ceramic/metal composite structure is also provided.

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Номер записи: 14

17-05-2012 дата публикации

Underfill method and chip package

Номер: US20120119353A1

Автор: Michael A. Gaynes, Rajneesh Kumar, Steve Ostrander, Thomas E. Lombardi

Принадлежит: International Business Machines Corp

A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

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Номер записи: 15

24-05-2012 дата публикации

Copper conductor film and manufacturing method thereof, conductive substrate and manufacturing method thereof, copper conductor wiring and manufacturing method thereof, and treatment solution

Номер: US20120125659A1

Автор: Hideo Nakako, Katsuyuki Masuda, Kazunori Yamamoto, Shunya Yokozawa, Yasushi Kumashiro, Yoshinori Ejiri, Youichi Machii

Принадлежит: Hitachi Chemical Co Ltd

Provided are a copper conductor film and manufacturing method thereof, and patterned copper conductor wiring, which have superior conductivity and wiring pattern formation, and with which there is no decrease in insulation between circuits, even at narrow wiring widths and narrow inter-wiring spacing. Disclosed are a copper conductor film and manufacturing method thereof in which a copper-based particle-containing layer, which contains both a metal having catalytic activity toward a reducing agent and copper oxide, is treated using a treatment solution that contains a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complex to form metallic copper in a single solution, and patterned copper conductor wiring that is obtained by patterning a copper-based particle-containing layer using printing and by said patterned particle-containing layer being treated by a treatment method using a solution that contains both a reagent that ionizes or complexes copper oxide and a reducing agent that reduces copper ions or copper complexes to form metallic copper in a single solution.

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Номер записи: 16

21-06-2012 дата публикации

Semiconductor package and manufacturing method therefor

Номер: US20120153509A1

Автор: Akihiko Tateiwa, Masahiro Kyozuka, Toru Hizume

Принадлежит: Shinko Electric Industries Co Ltd

According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

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Номер записи: 17

21-06-2012 дата публикации

Semiconductor chip assembly and method for making same

Номер: US20120155055A1

Автор: Belgacem Haba, Hiroaki Sato, Ilyas Mohammed, Kiyoaki Hashimoto, Norihito Masuda, Philip Damberg, Teck-Gyu Kang, Wei-Shun Wang, Yoshikuni Nakadaira

Принадлежит: Tessera LLC

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

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Номер записи: 18

28-06-2012 дата публикации

Method of Manufacturing a Printable Composition of a Liquid or Gel Suspension of Diodes

Номер: US20120164796A1

Автор: Brad Oraw, Eric Anthony Perozziello, Jeffrey Baldridge, Mark Allan Lewandowski, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, William Johnstone Ray

Принадлежит: NthDegree Technologies Worldwide Inc

An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary method of making a liquid or gel suspension of diodes comprises: adding a viscosity modifier to a plurality of diodes in a first solvent; and mixing the plurality of diodes, the first solvent and the viscosity modifier to form the liquid or gel suspension of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

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Номер записи: 19

13-09-2012 дата публикации

Thermally and dimensionally stable polyimide films and methods relating thereto

Номер: US20120231257A1

Автор: Brian C. Auman, Kostantinos Kourtakis, Meredith L. Dunbar, Tao He

Принадлежит: EI Du Pont de Nemours and Co

The present disclosure is directed to a polyimide film. The film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

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Номер записи: 20

13-09-2012 дата публикации

Coverlay compositions and methods relating thereto

Номер: US20120231263A1

Автор: Brian C. Auman, Kostantinos Kourtakis, Meredith L. Dunbar, Tao He

Принадлежит: EI Du Pont de Nemours and Co

The present disclosure is directed to a coverlay comprising a polyimide film and an adhesive layer. The polyimide film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

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Номер записи: 21

20-09-2012 дата публикации

Wiring substrate and method of manufacturing the same

Номер: US20120234589A1

Автор: Akihiko Tateiwa, Jun Furuichi, Naoyuki Koizumi

Принадлежит: Shinko Electric Industries Co Ltd

A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.

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Номер записи: 22

20-09-2012 дата публикации

Sensor module, sensor device, method for producing sensor device, and electronic apparatus

Номер: US20120236507A1

Автор: Yugo Koyama

Принадлежит: Seiko Epson Corp

A sensor module includes a supporting member having three support faces orthogonal to one another, three IC chips each having connection terminals and external connection terminals on the side thereof where an active face is located, the three IC chips attached to the support faces of the supporting member on the sides thereof where passive faces lying along the active faces are located, three vibrating gyro elements each having a base, vibrating arms extending from the base, and connection electrodes, and flexible wiring substrates connected to the external connection terminals of the IC chips, each vibrating gyro element is disposed on the side of the IC chip where the active face is located, the connection electrodes are attached to the connection terminals of each IC chip such that one principal surface lies along the support face, and the flexible wiring substrate has a reinforcing layer.

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Номер записи: 23

04-10-2012 дата публикации

Integrated circuit package including miniature antenna

Номер: US20120249380A1

Автор: Carles Puente Baliarda, Carmen Borja Borau, Jaume Anguera Pros, Jordi Soler Castany

Принадлежит: Fractus SA

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

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Номер записи: 24

25-10-2012 дата публикации

Sensor mounted in flip-chip technology on a substrate

Номер: US20120267731A1

Автор: Felix Mayer, Franziska Brem, Markus Graf, Werner Hunziker

Принадлежит: Individual

The sensor assembly comprises a substrate ( 1 ), such as a flexible printed circuit board, and a sensor chip ( 2 ) flip-chip mounted to the substrate ( 1 ), with a first side ( 3 ) of the sensor chip ( 2 ) facing the substrate ( 1 ). A sensing area ( 4 ) and contact pads ( 5 ) are integrated on the first side ( 3 ) of the sensor chip ( 2 ) and located in a chamber ( 17 ) between the substrate ( 1 ) and the sensor chip ( 2 ). Chamber ( 17 ) is bordered along at least two sides by a dam ( 16 ). Underfill ( 18 ) and/or solder flux is arranged between the sensor chip ( 2 ) and the substrate ( 1 ), and the dam ( 16 ) prevents the underfill from entering the chamber ( 17 ). An opening ( 19 ) extends from the chamber to the environment and is located between the substrate ( 1 ) and the sensor chip ( 2 ) or extends through the sensor chip ( 2 ).

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Номер записи: 25

06-12-2012 дата публикации

Stacked electronic component and manufacturing method thereof

Номер: US20120306103A1

Автор: Atsushi Yoshimura, Hideo Numata, Naoyuki Komuta

Принадлежит: Toshiba Corp

A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

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Номер записи: 26

13-12-2012 дата публикации

Semiconductor device structures

Номер: US20120313248A1

Автор: Mark E. Tuttle

Принадлежит: Micron Technology Inc

The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

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Номер записи: 27

20-12-2012 дата публикации

Module substrate, module-substrate manufacturing method, and terminal connection substrate

Номер: US20120320536A1

Автор: Issei Yamamoto

Принадлежит: Murata Manufacturing Co Ltd

In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

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Номер записи: 28

27-12-2012 дата публикации

Heating apparatus and annealing apparatus

Номер: US20120325795A1

Автор: Kazuhiro Ooya, Masatake Yoneda, Tomohiro Suzuki

Принадлежит: Tokyo Electron Ltd

A heating apparatus includes a heat dissipating board formed of a metal; an insulating layer directly formed on the heat dissipating board; a plurality of wiring elements which are arranged on the insulating layer in a wiring pattern; and a plurality of LED elements provided on the wiring elements, respectively. The heating apparatus further includes metal wiring lines which electrically connect the adjacent LED elements to each other in series.

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Номер записи: 29

31-01-2013 дата публикации

Semiconductor device, semiconductor module structure configured by vertically stacking semiconductor devices, and manufacturing method thereof

Номер: US20130026650A1

Автор: Akio Katsumata, Hiroshi Inoue, Osamu Yamagata, Satoru Itakura, Shigenori Sawachi, Yasuhiro Yamaji

Принадлежит: Individual

A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.

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Номер записи: 30

07-02-2013 дата публикации

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

Номер: US20130032938A1

Автор: Charles W.C. Lin, Chia-Chung Wang

Принадлежит: Individual

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

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Номер записи: 31

14-02-2013 дата публикации

Fabrication method of packaging substrate having through-holed interposer embedded therein

Номер: US20130040427A1

Автор: Dyi-chung Hu, Tzyy-Jang Tseng, Yu-Shan Hu

Принадлежит: Unimicron Technology Corp

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

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Номер записи: 32

07-03-2013 дата публикации

Surface acoustic wave device and production method therefor

Номер: US20130057361A1

Автор: Kiwamu Sakano, Shu Yamada

Принадлежит: Murata Manufacturing Co Ltd

A surface acoustic wave device includes a surface acoustic wave element including a plurality of electrode pads, and a mount substrate. The surface acoustic wave element is flip-chip mounted on a die-attach surface of the mount substrate by bumps made of Au. The mount substrate includes at least one resin layer including via-holes, a plurality of mount electrodes provided on the die-attach surface of the mount substrate, and via-hole conductors. The mount electrodes are bonded to the electrode pads via the bumps. The via-hole conductors are provided in the via-holes. At least one of each of the electrode pads and each of the mount electrodes includes a front layer made of Au. At least one of the via-hole conductors is located below the corresponding bump.

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Номер записи: 33

07-03-2013 дата публикации

Electronic component and method for producing same

Номер: US20130058061A1

Автор: Atsushi Nagai, Minoru Satoh, Takehiro Yamashita, Yasuo Adachi

Принадлежит: Noritake Co Ltd, TDK Corp

This electronic component is provided with an inorganic substrate, a conductor film formed on a surface of the substrate, and bonding wires bonded to a part of said conductor film, and wire bonding sections are formed on at least a part of the electronic component. The part of the conductor film at least forming the aforementioned wire bonding sections contains an Ag-based metal formed of Ag or an alloy having Ag as the main constituent and a metal oxide which coats said Ag-based metal and which has, as a constituent element, any of the elements selected from the group consisting of Al, Zr, Ti, Y, Ca, Mg, and Zn. The coating quantity of the metal oxide is a quantity corresponding to 0.02 to 0.1 parts by mass relative to 100 parts by mass of the aforementioned Ag-based metal.

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Номер записи: 34

28-03-2013 дата публикации

Stacked semiconductor apparatus, system and method of fabrication

Номер: US20130077374A1

Автор: Kang-Wook Lee, Ki-tae Park, Young-don Choi, Yun-sang Lee

Принадлежит: Individual

A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

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Номер записи: 35

28-03-2013 дата публикации

Method for manufacturing semiconductor apparatus

Номер: US20130078766A1

Автор: Akira Tojo, Kentaro Suga, Takao Nogi, Tomoyuki Kitani

Принадлежит: Individual

A method for manufacturing a semiconductor apparatus includes: forming a protrusion made of a conductor on each of the electrodes provided on a semiconductor wafer top face side of a plurality of semiconductor devices formed in a semiconductor wafer; making a trench in the top face between the plurality of semiconductor devices; filling an insulator into a gap between the protrusions and into the trench to form a sealing member; grinding a bottom face of the semiconductor wafer opposing the top face until the sealing member being exposed to divide the semiconductor wafer into each of the semiconductor devices; forming a first lead made of a conductor on each of the protrusions, the first lead forming a portion of a first external electrode; and forming a conductive material layer directly to form a second lead on the bottom face of the plurality of semiconductor devices.

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Номер записи: 36

18-04-2013 дата публикации

Fixing material comprising silane compound polymer and photonic device sealed body

Номер: US20130096253A1

Автор: Mikihiro Kashio, Takashi Tamada

Принадлежит: Lintec Corp

A fixing material includes a silane compound polymer as the main component, the silane compound polymer being produced by condensing a silane compound mixture that includes at least one silane compound (1) shown by the following formula (1): R 1 Si(OR 2 ) p (X 1 ) 3-p (wherein R 1 represents a group including an ester structure or a cyanoalkyl group, R 2 represents an alkyl group having 1 to 6 carbon atoms or the like, X 1 represents a halogen atom, and p is an integer from 0 to 3), and at least one silane compound (2) shown by the following formula (2): Si(OR 3 ) q (X 2 ) 4-q (wherein R 3 represents an alkyl group having 1 to 6 carbon atoms, X 2 represents a halogen atom, and q is an integer from 0 to 4). A sealed optical device includes an optical device that is sealed with a cured product of the fixing material. The fixing material produces a cured product that exhibits high hardness, excellent transparency and heat resistance, and rarely undergoes coloration even when subjected to high-energy light or heat for a long time.

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Номер записи: 37

30-05-2013 дата публикации

Film forming method and processing system

Номер: US20130136859A1

Автор: Hitoshi Itoh, Kenji Matsumoto, Shigetoshi Hosaka

Принадлежит: Tokyo Electron Ltd

A film forming method performs a film forming process on a target object having on a surface thereof an insulating layer. The film forming method includes a first thin film forming step of forming a first thin film containing a first metal, an oxidation step of forming an oxide film by oxidizing the first thin film, and a second thin film forming step of forming a second thin film containing a second metal on the oxide film.

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Номер записи: 38

06-06-2013 дата публикации

Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same

Номер: US20130140715A1

Автор: Clinton Chao, Shin-puu Jeng, Szu Wei Lu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

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Номер записи: 39

22-08-2013 дата публикации

Package-in-Package Using Through-Hole Via Die on Saw Streets

Номер: US20130214385A1

Автор: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

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Номер записи: 40

05-09-2013 дата публикации

Semiconductor device structures and printed circuit boards comprising semiconductor devices

Номер: US20130228922A1

Автор: Mark E. Tuttle

Принадлежит: Micron Technology Inc

The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

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Номер записи: 41

19-09-2013 дата публикации

Electronic component element housing package

Номер: US20130240262A1

Автор: Masanori Nagahiro

Принадлежит: Nippon Steel and Sumikin Electronics Devices Inc

An electronic component element housing package is produced by firing a ceramic substrate for housing an electronic component element and a metal layer for bonding to the ceramic substrate to form an electrical path, simultaneously in a reducing atmosphere. The ceramic substrate comprises alumina (Al 2 O 3 ), a partially stabilized zirconia by forming solid solution with yttria (Y 2 O 3 ) and a sintering agent. The sintering agent comprises magnesia (MgO), and at least 1 type selected from silica (SiO 2 ), calcia (CaO), or manganese oxides (MnO, MnO 2 , Mn 2 O 3 , Mn 3 O 4 ).

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Номер записи: 42

26-09-2013 дата публикации

Thin film forming method

Номер: US20130252417A1

Автор: Atsushi Gomi, Chiaki Yasumuro, Hiroaki Kawasaki, Jonathan Rullan, Osamu Yokoyama, Tadahiro Ishizaka, Takara KATO, Tatsuo Hatano

Принадлежит: Tokyo Electron Ltd

A thin film forming method in which a thin film is formed on a surface of a target object to be processed to fill a recess formed in the surface of the target object includes the steps of forming a metal layer for filling on the surface of the target object to fill the recess formed in the surface of the target object and forming a metal film for preventing diffusion on an entire surface of the target object to cover the metal layer for filling. The thin film forming method further includes the step of annealing the target object having the metal film for preventing diffusion formed thereon.

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Номер записи: 43

10-10-2013 дата публикации

Semiconductor device

Номер: US20130264605A1

Автор: Masataka Muto, Mitsuhiko Ogihara, Takahito Suzuki, Tomohiko Sagimori

Принадлежит: Oki Data Corp

A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.

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Номер записи: 44

10-10-2013 дата публикации

Semiconductor Package and Method of Manufacturing the Same

Номер: US20130264706A1

Автор: Dong-Hyeon Jang, Ho-geon Song, Sung-Jun IM, Teak-Hoon LEE, Won-Keun Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

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Номер записи: 45

07-11-2013 дата публикации

Method for forming a copper wiring pattern

Номер: US20130295276A1

Автор: Hideo Nakako, Katsuyuki Masuda, Kazunori Yamamoto, Shunya Yokozawa, Yasushi Kumashiro, Yoshinori Ejiri, Youichi Machii

Принадлежит: Hitachi Chemical Co Ltd

There is provided a method wherein a surface treating agent, which is essential for making copper particles antioxidative and dispersing the copper particles in the prior art, is hardly used, but copper particles, which cause little electromigration and are small in the price rate of material itself, are used to form a low-resistance copper wiring pattern while the generation of cracks therein is restrained. The method includes the step of using a dispersion slurry wherein copper based particles having a copper oxide surface are dispersed to form any pattern over a substrate, and the step of reducing the copper oxide surface of the copper based particles in the pattern with atomic form hydrogen to return the oxide to copper, and sintering particles of the copper metal generated by the reduction and bonding the particles to each other.

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Номер записи: 46

28-11-2013 дата публикации

Semiconductor integrated circuit device

Номер: US20130313708A1

Автор: Akira Yajima, Hiromi Shigihara, Hiroshi Tsukamoto

Принадлежит: Renesas Electronics Corp

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

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Номер записи: 47

28-11-2013 дата публикации

Substrate for semiconductor package and method of manufacturing thereof

Номер: US20130316495A1

Автор: Akinobu Shibuya, Akira Ouchi

Принадлежит: NEC Corp

Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.

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Номер записи: 48

26-12-2013 дата публикации

Package substrate and die spacer layers having a ceramic backbone

Номер: US20130341076A1

Автор: Aleksandar Aleksov, Shankar Ganapathysubramanian, Sujit Sharan, Vladimir Noveski

Принадлежит: Individual

A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

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Номер записи: 49

26-12-2013 дата публикации

Miniature Surface Mount Device

Номер: US20130341656A1

Автор: Chak Hau Pang, Chi Keung Chan, David Todd Emerson, Fei Hong Li

Принадлежит: Cree Inc

A surface mount LED package includes a lead frame carrying a plurality of LEDs and a plastic casing at least partially encasing the lead frame. The lead frame includes an electrically conductive chip carrier and first, second, and third electrically conductive connection parts separate from the electrically conductive chip carrier. Each of the first, second and third electrically conductive connection parts has an upper surface, a lower surface, and a connection pad on the upper surface. The plurality of LEDs are disposed on an upper surface of the electrically conductive chip carrier. Each LED has a first electrical terminal electrically coupled to the electrically conductive chip carrier. Each LED has a second electrical terminal electrically coupled to the connection pad of a corresponding one of the first, second, and third electrically conductive connection parts.

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Номер записи: 50

26-12-2013 дата публикации

Simultaneous wafer bonding and interconnect joining

Номер: US20130341804A1

Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian

Принадлежит: Tessera LLC

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

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Номер записи: 51

06-02-2014 дата публикации

Cased electrical component

Номер: US20140036466A1

Автор: Jürgen Portmann, Wolfgang Pahl

Принадлежит: EPCOS AG

The invention relates to a cased electrical component comprising a carrier substrate ( 10 ), a spring device ( 20 ), which is arranged on the carrier substrate ( 10 ), a chip ( 30 ), which on a first side ( 31 ) of the chip is coupled to the spring device ( 20 ), and a cover element ( 100 ), which is arranged on the carrier substrate ( 10 ). The cover element ( 100 ) is arranged over the chip ( 20 ) such that the cover element ( 100 ) is in contact with the chip ( 30 ) at least on a second side ( 32 ) of the chip, which is different from the first side. The component has a low space requirement and is highly sealed with respect to influences from the surroundings.

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Номер записи: 52

13-02-2014 дата публикации

Fluid storage and dispensing system including dynamic fluid monitoring of fluid storage and dispensing vessel

Номер: US20140041440A1

Автор: Frank DiMeo, Jr., James Dietz, James V. McManus, Michael J. Wodjenski, Robert Kaim, Steven E. Bishop, Steven M. Lurcott

Принадлежит: Advanced Technology Materials Inc

A monitoring system for monitoring fluid in a fluid supply vessel during operation including dispensing of fluid from the fluid supply vessel. The monitoring system includes (i) one or more sensors for monitoring a characteristic of the fluid supply vessel or the fluid dispensed therefrom, (ii) a data acquisition module operatively coupled to the one or more sensors to receive monitoring data therefrom and responsively generate an output correlative to the characteristic monitored by the one or more sensors, and (iii) a processor and display operatively coupled with the data acquisition module and arranged to process the output from the data acquisition module and responsively output a graphical representation of fluid in the fluid supply vessel, billing documents, usage reports, and/or resupply requests.

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Номер записи: 53

20-02-2014 дата публикации

Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure

Номер: US20140048932A1

Автор: Reza A. Pagaila

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

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Номер записи: 54

06-03-2014 дата публикации

Devices and methods

Номер: US20140061584A1

Автор: Gagan Mahan, Peter T. Kazlas

Принадлежит: QD Vision Inc

A device comprising an arrangement of device materials and a layer comprising a material with heat-dissipating properties disposed over at least a portion thereof is disclosed. The device can further include an interleave layer disposed between the top surface of the arrangement of device materials and the layer comprising a material with heat-dissipating properties. A barrier layer may further be included between the arrangement of device materials and the layer comprising a material with heat-dissipating properties. Methods are also disclosed. In certain embodiments, a device includes quantum confined semiconductor nanoparticles.

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Номер записи: 55

06-03-2014 дата публикации

Multi-Chip Module and Method of Manufacture

Номер: US20140061895A1

Автор: Cheng Sim Kee, Lay Hong LEE, Mohamed Suhaizal Bin Abu-Hassan, Yin Lye Foong

Принадлежит: SPANSION LLC

A multi-chip module and a method for manufacturing the multi-chip module that mitigates wire breakage. A first semiconductor chip is mounted and wirebonded to a support substrate. A spacer is coupled to the first semiconductor chip. A support material is disposed on the spacer and a second semiconductor chip is positioned on the support material. The second semiconductor chip is pressed into the support material squeezing it into a region adjacent the spacer and between the first and second semiconductor chips. Alternatively, the support material is disposed on the first semiconductor chip and a die attach material is disposed on the spacer. The second semiconductor chip is pressed into the die attach material and the support material, squeezing a portion of the support material over the spacer edges. Wirebonds are formed between the support substrate and the first and second semiconductor chips.

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Номер записи: 56

20-03-2014 дата публикации

Compliant printed circuit semiconductor package

Номер: US20140080258A1

Автор: James Rathburn

Принадлежит: HSIO Technologies LLC

A method of making a package for a semiconductor device having electrical terminals. At least one semiconductor device is located on a substrate. A first dielectric layer is printed on at least a portion of the semiconductor device to include first recesses aligned with a plurality of the electrical terminals. A conductive material is deposited in the first recesses forming contact members. A second dielectric layer is printed on at least a portion of the first dielectric layer to include second recesses aligned with a plurality of the first recesses. A conductive material is deposited in at least a portion of the second recesses to include a circuit geometry and a plurality of exposed terminals. A compliant material is deposited in recesses in one or more of the first and second dielectric layers adjacent to a plurality of the exposed terminals.

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Номер записи: 57

10-04-2014 дата публикации

Compliant interconnects in wafers

Номер: US20140099754A1

Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian

Принадлежит: Tessera LLC

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

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Номер записи: 58

04-01-2018 дата публикации

Method of Joining Metal-Ceramic Substrates to Metal Bodies

Номер: US20180002239A1

Автор: Knoll Heiko

Принадлежит:

A method of joining a metal-ceramic substrate having metalization on at least one side to a metal body by using a metal alloy is disclosed. The metal body has a thickness of less than 1.0 mm, and the metal alloy contains aluminum and has a liquidus temperature of greater than 450° C. The resulting metal-ceramic module provides a strong bond between the metal body and the ceramic substrate. The resulting module is useful as a circuit carrier in electronic appliances, with the metal body preferably functioning as a cooling body. 112-. (canceled)13. A module comprising:a metal-ceramic substrate having metalization on at least one side, wherein the metal-ceramic substrate is adapted to have a semiconductor component disposed on at least one metalized side of the metal-ceramic substrate, and wherein the metal-ceramic substrate includes a ceramic substrate and no more than two metal layers each of which directly contacts the ceramic substrate;a metal body having a thickness of less than 1 mm; anda joining region joining the ceramic substrate to the metal body, the joining region including a metal alloy containing aluminum and having a liquidus temperature of greater than 450° C.14. The module of claim 13 , wherein the peeling force required for separating the metal-ceramic substrate from the metal body is greater than 3 N/mm.15. The module of used as a circuit carrier in an electronic appliance.16. The module of claim 13 , wherein a surface of the metal-ceramic substrate that contacts the metal alloy has a first surface area claim 13 , wherein a surface of the metal body that contacts the metal alloy has a second surface area claim 13 , and wherein the first surface area is smaller than the second surface area.17. The module of claim 13 , wherein the metal alloy further comprises silicon.18. The module of claim 13 , wherein the metal alloy further comprises magnesium.19. The module of claim 13 , wherein based on the total weight of the metal alloy claim 13 , the metal ...

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Номер записи: 59

11-01-2018 дата публикации

METHIOD OF MANUFACTURING AN IMPLANTABLE ELECTRODE ARRAY BY FORMING PACKAGES AROUND THE ARRAY CONTROL MODULES AFTER THE CONTROL MODULES ARE BONDED TO SUBSTRATES

Номер: US20180008818A1

Автор: Brindley Robert, Dunlop James Bernard, Janik John, Spangler Joseph Leland, Tang Edward Chia-Ning

Принадлежит:

A method of forming an implantable electrode array that includes one or more packaged control modules. A control module is packaged by mounting the module to a substrate and forming a containment ring around the module. A conformal coating is disposed over the surface of the module to cover the carrier. Within the containment ring, the conformal coating hardens to form a non-porous shell around the control module. The one or more packaged control modules are placed in a flexible array. Electrodes that are mounted to or embedded in the flexible carrier are connected to the one or more control modules. 1. A method of assembling an implantable electrode array , said method including the steps of: forming a containment ring on a first surface of a substrate;', 'mounting a control module to the first surface of the substrate so that the control module is disposed in the containment ring;', 'applying a coating to the first surface of the substrate so that the coating is disposed in the containment ring around the control module so that the coating forms a non-porous shell in the containment ring around the control module;', 'bonding a lid over the containment ring so that the lid extends over the control module and the shell so as to form at least one packaged control module, 'packaging at least one control module according to the steps ofembedding the at least one packaged control module in a flexible carrier; andelectrically connecting the at least one packaged control module to at least one electrode that is disposed over or embedded in the flexible carrier.2. The method of assembling an implantable electrode array of claim 1 , wherein: said step of forming a containment ring of the first surface of the substrate is performed by forming the containment ring so that the containment ring is at least partially located inwardly of an outer perimeter of the containment ring;', 'in said step of applying a coating to the first surface of the substrate, the coating is applied ...

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Номер записи: 60

09-01-2020 дата публикации

Illumination apparatus

Номер: US20200011510A1

Автор: Harrold Jonathan, Woodgate Graham J.

Принадлежит:

An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array. 1. A method for providing an illumination apparatus , comprising:selectively removing a plurality of light-emitting elements from a monolithic array of light-emitting elements in a manner that preserves the relative spatial position of the selectively removed light-emitting elements;forming a non-monolithic array of light-emitting elements with the removed plurality of light-emitting elements in a manner that preserves the relative spatial position of the selectively removed light-emitting elements;determining a group of light-emitting elements of the non-monolithic array which fails at least one functional criterion; andchanging an electrical drive to at least one light-emitting element of the non-monolithic array such that the group of light-emitting elements which failed the at least one functional criterion passes the at least one functional criterion following the change.2. The method according to claim 1 , wherein the plurality of light-emitting elements that are selectively removed from the monolithic array are selected such that claim 1 , in at least one direction claim 1 , for at least one pair of the selectively removed light-emitting elements in the at least one direction claim 1 , for each respective pair there is at least one respective light-emitting element that is not selected that was positioned in the monolithic array between the pair of removed light-emitting elements in the at least one direction.3. The method according to claim 1 , wherein changing the electrical drive comprises creating or removing a short ...

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Номер записи: 61

25-01-2018 дата публикации

Apparatus with Light Emitting or Absorbing Diodes

Номер: US20180023793A1

Автор: Brad Oraw, Eric Anthony Perozziello, Jeffrey Baldridge, Mark Allan Lewandowski, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, William Johnstone Ray

Принадлежит: NthDegree Technologies Worldwide Inc

An exemplary printable composition of a liquid or gel suspension of diodes generally includes a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary apparatus may include: a plurality of diodes; at least a trace amount of a first solvent; and a polymeric or resin film at least partially surrounding each diode of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

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Номер записи: 62

25-01-2018 дата публикации

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

Номер: US20180025967A1

Автор: Belgacem Haba, Richard DeWitt Crisp, Wael Zohni

Принадлежит: Tessera LLC

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

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Номер записи: 63

25-01-2018 дата публикации

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

Номер: US20180026023A1

Автор: KANG Chen, Seung Wook Yoon, Yaojian Lin

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

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Номер записи: 64

29-01-2015 дата публикации

SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASED POST HEIGHT

Номер: US20150028480A1

Автор: Damberg Philip, Haba Belgacem, Sakuma Kazuo

Принадлежит:

An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces. 1. An interconnection substrate , comprising:a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions;electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, the conductive projections extending from the conductive elements above the at least one wiring layer, the conductive projections having end portions remote from the conductive elements and neck portions between the conductive elements and the end portions, the end portions having lower surfaces extending outwardly from the neck portions in at least one of the lateral directions; anda dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces, at least portions of the dielectric layer between the conductive projections being recessed below a height of the lower surfaces.2. The substrate of claim 1 , wherein the dielectric layer is a solder mask.3. The substrate of claim 1 , ...

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Номер записи: 65

29-01-2015 дата публикации

Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure

Номер: US20150028496A1

Автор: Henry D. Bathan, Jairus L. Pisigan, Zigmund R. Camacho

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

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Номер записи: 66

24-01-2019 дата публикации

Light emitting apparatus

Номер: US20190027667A1

Автор: Ryohei Yamashita, Ryoichi Yoshimoto

Принадлежит: Nichia Corp

A light emitting apparatus includes a positive lead terminal and a negative lead terminal, each of which includes a first main surface, a second main surface, and an end surface including a first recessed surface area extending from a first point of the first main surface in cross section, and a second recessed surface area extending from a second point of the second main surface in cross section. A distance between a first part of the end surface of the positive lead terminal and a second part of the end surface of the negative lead terminal than a first distance between the first points of the positive lead terminal and the negative lead terminal and a second distance between the second points of the positive lead terminal and the negative lead terminal. The first part and the second part are separated from the first point and the second point.

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Номер записи: 67

23-01-2020 дата публикации

Integrated Circuit Package Including Miniature Antenna

Номер: US20200028264A1

Автор: Anguera Pros Jaume, Borja Borau Carmen, Puente Baliarda Carles, Soler Castany Jordi

Принадлежит:

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115°, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna. 1. A wireless system comprising:a substrate;a chip mounted on the substrate;a sensor mounted on the substrate;a first antenna mounted on the substrate and enclosed in a first rectangular area that does not enclose the chip, the first antenna comprising a first conducting pattern having a perimeter, wherein the perimeter of the first conducting pattern defines a first curve comprising at least five segments, wherein: each of the at least five segments forms an angle with each adjacent segment, at least three of the segments are smaller than a tenth of a longest free-space operating wavelength of the first antenna, each angle between adjacent segments is less than 180°, and at least two of the angles between adjacent segments are less than 115°; anda second antenna mounted on the substrate and enclosed in a second rectangular area having a longer side shorter than one-fifth of a longest free-space operating ...

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Номер записи: 68

01-02-2018 дата публикации

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

Номер: US20180033754A1

Автор: Dugas Roger, Trezza John

Принадлежит:

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface. 1. A method comprising:constraining a portion of multiple chips adjacent a hardened material such that the hardened material and the multiple chips behave as a rigid body;transferring a force from the hardened material on the rigid body to the multiple chips to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element, without causing damage to the multiple chips or the bonding surface of the element; andremoving the hardened material from contact with the multiple chips.2. The method of claim 1 , further comprising moving the multiple chips constrained by the hardened material from a first location to a second location.3. The method of claim 1 , further comprising bonding each of the multiple chips to the element.4. The method of claim 1 , further comprising removing the rigid body using at least one of a chemical process claim 1 , a mechanical process claim 1 , or a chemical-mechanical process.5. The method of claim 1 , further comprising removing at least a portion of the hardened material through at least one of a chemical process claim 1 , a mechanical process claim 1 ...

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Номер записи: 69

12-02-2015 дата публикации

Fan-Out WLP With Package

Номер: US20150044824A1

Автор: Belgacem Haba, Hiroaki Sato, Ilyas Mohammed, Kiyoaki Hashimoto, Norihito Masuda, Philip Damberg, Yoshikuni Nakadaira

Принадлежит: Tessera LLC

The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and electrically connecting redistribution contacts on the microelectronic unit and terminals on the substrate with a conductive matrix material extending within at least one opening extending through the substrate.

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Номер записи: 70

15-05-2014 дата публикации

Micro-reflectors on a substrate for high-density led array

Номер: US20140131755A1

Автор: Alexander F. Schreiner, Duwayne R. Anderson, Mark D. Owen, THOMAS R. McNEILL

Принадлежит: Phoseon Technology Inc

The present invention provides an optical array module that includes a plurality of semiconductor devices mounted on a thermal substrate formed with a plurality of openings that function as micro-reflectors, wherein each micro-reflector includes a layer of reflective material to reflect light. Such material preferably is conductive so as to provide electrical connection for its associated semiconductor device.

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Номер записи: 71

22-02-2018 дата публикации

CASED ELECTRICAL COMPONENT

Номер: US20180054886A1

Автор: Pahl Wolfgang, Portmann Jürgen

Принадлежит:

The invention relates to a cased electrical component comprising a carrier substrate (), a spring device (), which is arranged on the carrier substrate (), a chip (), which on a first side () of the chip is coupled to the spring device (), and a cover element (), which is arranged on the carrier substrate (). The cover element () is arranged over the chip () such that the cover element () is in contact with the chip () at least on a second side () of the chip, which is different from the first side. The component has a low space requirement and is highly sealed with respect to influences from the surroundings. 1. A method for producing a cased electrical component , comprising:providing a carrier substrate;arranging a spring device on the carrier substrate;arranging a chip on the spring device in such a way that a first side of the chip is coupled to the spring device; andarranging a covering element over the chip in such a way that the covering element touches the chip at least at a second side of the chip, the second side being different from the first side.2. The method according to claim 1 , wherein arranging the spring device on the carrier substrate comprises:sputtering and electrodepositing a first layer on the carrier substrate;sputtering and electrodepositing a second layer on an end section of the first layer and on a photoresist; andremoving the photoresist below the second layer.3. The method according to claim 2 , further comprising arranging a bearing element on the carrier substrate by:sputtering and electrodepositing a third layer on the carrier substrate; andmechanically post-processing the third layer in such a way that the third layer has a planar surface suitable for bearing for the chip.4. The method according to claim 3 , further comprising arranging the covering element on the carrier substrate by:laminating a film composed of a material composed of plastic over the chip and the carrier substrate; andsputtering and electrodepositing a fourth ...

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Номер записи: 72

22-05-2014 дата публикации

Diode for a Printable Composition

Номер: US20140138666A1

Автор: Brad Oraw, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, William Johnstone Ray

Принадлежит: NthDegree Technologies Worldwide Inc

An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary diode comprises: a light emitting or absorbing region having a diameter between about 20 and 30 microns and a height between about 2.5 to 7 microns; a first terminal coupled to the light emitting region on a first side, the first terminal having a height between about 1 to 6 microns; and a second terminal coupled to the light emitting region on a second side opposite the first side, the second terminal having a height between about 1 to 6 microns.

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Номер записи: 73

22-05-2014 дата публикации

Semiconductor device and production method therefor

Номер: US20140141550A1

Автор: Masafumi Kuramoto, Miki Niwa, Satoru Ogawa

Принадлежит: Nichia Corp

An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.

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Номер записи: 74

10-03-2016 дата публикации

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE

Номер: US20160071777A1

Автор: Ikeda Hikaru, UNO TAKASHI, Yahata Kazuhiro

Принадлежит:

A semiconductor package or a semiconductor device includes a heat sink onto which a semiconductor or a matching circuit is to be placed, a lead terminal which is to be electrically-connected to the semiconductor or the matching circuit on the heat sink, and a securing member which secures the lead terminal to the heat sink, wherein the securing member is formed by a composite resin material in which a resin and a ceramic powder are mixed. 1. A semiconductor package comprising:a heat sink which is a conductive plate and onto which a semiconductor or a matching circuit is to be placed;a lead terminal which is to be electrically-connected to the semiconductor or the matching circuit on the heat sink; anda securing member which secures the lead terminal to the heat sink, whereinthe securing member is formed by a composite resin material in which an epoxy resin and a ceramic powder are mixed, and whereinthe securing member is disposed to contact with an oxidized contact surface of the heat sink and an oxidized part has been removed from the heat sink other than the oxidized contact surface.2. The semiconductor package according to claim 1 , wherein the securing member has a thickness larger than that of the semiconductor or the matching circuit on the heat sink claim 1 , and the heat sink and the securing member define a cavity to accommodate the semiconductor or the matching circuit.3. The semiconductor package according to claim 1 , wherein a glass-transition temperature of the resin mixed in the composite resin material forming the securing member is lower than a heating temperature under which the semiconductor or the matching circuit is bonded onto the heat sink.4. The semiconductor package according to claim 1 , wherein the heat sink or the lead terminal has a roughened part in a position to have contact with the securing member.5. The semiconductor package according to claim 1 , wherein the lead terminal has an oxidized part in a position to have contact with the ...

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Номер записи: 75

08-03-2018 дата публикации

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE INCLUDING METAL PATTERNS AND CUT-OUT SECTION

Номер: US20180069160A1

Автор: KAMADA Kazuhiro

Принадлежит: NICHIA CORPORATION

A light emitting device includes a substrate; a light emitting element mounted on an upper surface of the substrate; a light-reflecting member surrounding lateral surfaces of the light emitting element; and a sealing member disposed over an upper surface of the light emitting element and an upper surface of the light-reflecting member. An outer edge of the upper surface of the light-reflecting member coincides with an outer edge of a lower surface of the sealing member. 1. A light emitting device comprising:a substrate;a light emitting element mounted on an upper surface of the substrate;a light-reflecting member surrounding lateral surfaces of the light emitting element; anda sealing member disposed over an upper surface of the light emitting element and an upper surface of the light-reflecting member,wherein an outer edge of the upper surface of the light-reflecting member coincides with an outer edge of a lower surface of the sealing member.2. The light emitting device according to claim 1 ,wherein an inner edge of the upper surface of the light-reflecting member is located higher than the outer edge in the height direction, andwherein the upper surface of the light-reflecting member is a concave curved surface.3. The light emitting device according to claim 1 , wherein the substrate comprises a first metal part and a second metal part at the upper surface of the substrate.4. The light emitting device according to claim 3 , wherein claim 3 , in a plan view claim 3 , the second metal part is located at a center of the substrate and is sandwiched by two portions of the first metal part.5. The light emitting device according to claim 3 ,wherein the light emitting element comprises a first electrode and a second electrode on a same surface, andwherein the light emitting element is mounted on the substrate upper surface such that the first electrode of the light emitting element faces the first metal part of the substrate, and the second electrode of the light ...

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Номер записи: 76

23-03-2017 дата публикации

Method of manufacturing light emitting device including metal patterns and cut-out section

Номер: US20170084794A1

Автор: Kazuhiro Kamada

Принадлежит: Nichia Corp

A light emitting device includes a support member having a mounting surface. The support member includes an insulating member having top surface and a plurality of side surfaces, a first metal pattern disposed on the top surface of the insulating member, and a second metal pattern disposed on the side surface of the insulating member such that a side surface of the second metal pattern is continuous with a top surface of the first metal pattern. The light emitting device further includes a light emitting element mounted on the mounting surface at a location of the first metal pattern, and a bonding member that bonds the light emitting element to the mounting surface. The bonding member covers at least a portion of the first metal pattern and at least a portion of the second metal pattern.

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Номер записи: 77

03-07-2014 дата публикации

Three-dimensional structure in which wiring is provided on its surface

Номер: US20140183751A1

Автор: Hiroaki Fujiwara, Hiromitsu Takashita, Shingo Yoshioka, Tsuyoshi Takeda

Принадлежит: Panasonic Corp

One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

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Номер записи: 78

13-04-2017 дата публикации

Illumination apparatus

Номер: US20170102127A1

Автор: Graham John Woodgate, Jonathan Harrold

Принадлежит: Optovate Ltd

An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.

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Номер записи: 79

10-07-2014 дата публикации

Hybrid combination of substrate and carrier mounted light emitting devices

Номер: US20140191254A1

Автор: Serge J. Bierhuizen

Принадлежит: Koninklijke Philips N.V

A multi-chip light emitting device (LED) uses a low-cost carrier structure that facilitates the use of substrates that are optimized to support the devices that require a substrate. Depending upon the type of LED elements used, some of the LED elements may be mounted on the carrier structure, rather than on the more expensive ceramic substrate. In like manner, other devices, such as sensors and control elements, may be mounted on the carrier structure as well. Because the carrier and substrate structures are formed independent of the encapsulation and other after-formation processes, these structures can be tested prior to encapsulation, thereby avoiding the cost of these processes being applied to inoperative structures.

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Номер записи: 80

24-07-2014 дата публикации

Integrated Circuit Structures, Semiconductor Structures, And Semiconductor Die

Номер: US20140203409A1

Автор: Gurtej S. Sandhu, Kristina K. Parat

Принадлежит: Micron Technology Inc

Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.

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Номер записи: 81

24-07-2014 дата публикации

Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core

Номер: US20140203443A1

Автор: Byung Tai Do, Reza A. Pagaila, Shuangwu Huang

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

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Номер записи: 82

14-05-2015 дата публикации

Integrated antenna for rfic package applications

Номер: US20150129668A1

Автор: Dong G. Kam, DUIXIAN LlU, Scott K. Reynolds

Принадлежит: International Business Machines Corp

A chip package includes a set of layers including conductive planes connected by vias. A first portion has at least one antenna, antenna ground plane, and first grounded vias. A second portion has a conductive plane parallel to the ground plane that forms an interface for connecting to at least one integrated circuit device. A third portion between the first and the second portion has a vertical transmission line that includes a signal via connecting the antenna feed line to the at least one integrated circuit and a parallel-plate mode suppression mechanism. The parallel-plate mode suppression mechanism includes a grounded reflector that forms a cage with the grounded vias around an antenna region and further includes second ground vias surrounding the signal via.

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Номер записи: 83

03-05-2018 дата публикации

LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE

Номер: US20180123006A1

Автор: KAMADA Kazuhiro, Seno Ryota, YAMADA Motokazu

Принадлежит: NICHIA CORPORATION

A light emitting device () includes a base member (), electrically conductive members () disposed on the base member (), a light emitting element () mounted on the electrically conductive members (), an insulating filler () covering at least a portion of surfaces of the electrically conductive members () where the light emitting element () is not mounted, and a light transmissive member () covering the light emitting element (). 1. A light emitting device comprising:a light emitting element having a semiconductor layer and a transparent substrate;a reflective member exposing at least apart of side surfaces and a top surface of the transparent substrate and covering side surfaces of the semiconductor layer; anda light transmissive member covering a portion of the transparent substrate exposed from the reflective member.2. The light emitting device according to further comprising a base member and electrically conductive members disposed on the base member claim 1 , wherein the light emitting element is mounted on the electrically conductive members claim 1 , at a surface of the electrically conductive members claim 1 , at least a portion of which does not have the light emitting element mounted thereon is covered with an insulating filler which is the reflective member claim 1 , and the light transmissive member covers the light emitting element.3. The light emitting device according to claim 2 , wherein the base member has a recess and the electrically conductive members are disposed on a bottom surface and side surfaces of the recess claim 2 , and the light emitting element is mounted on the bottom surface of the recess.4. The light emitting device according to claim 3 , wherein the side surfaces of the recess has claim 3 , at a portion abutting on a top edge surface of the recess have a region where an electrically conductive member is not formed.5. The light emitting device according to claim 3 , wherein the side surfaces of the recess at a portion abutting on ...

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Номер записи: 84

25-04-2019 дата публикации

SEMICONDUCTOR PACKAGE INCLUDING ORGANIC INTERPOSER

Номер: US20190122949A1

Автор: Lee Dong Hun

Принадлежит:

A semiconductor package including an organic interposer includes: the organic interposer including insulating layers and wiring layers formed on the insulating layers; a stiffener disposed on the interposer and having a through-hole; a first semiconductor chip disposed in the organic through-hole on the organic interposer; a second semiconductor chips disposed adjacent to the first semiconductor chip in the through-hole on the organic interposer; and an underfill resin filling at least portions of the through-hole and fixing the first semiconductor chip and the second semiconductor chip, wherein the connection pads of the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the wiring layers of the organic interposer. 1. A semiconductor package , comprising:an organic interposer including insulating layers and wiring layers formed on the insulating layers;a stiffener disposed on the organic interposer and having a through-hole;a first semiconductor chip disposed in the through-hole on the organic interposer and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;a second semiconductor chip disposed adjacent to the first semiconductor chip in the through-hole on the organic interposer, the second semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surfaces; andan underfill resin filling at least portions of the through-hole and fixing the first semiconductor chip and the second semiconductor chip,wherein the connection pads of the first semiconductor chip and the plurality of second semiconductor chips are electrically connected to each other through the wiring layers of the organic interposer.2. The semiconductor package of claim 1 , wherein the second semiconductor chip comprises a plurality of second semiconductor chips claim 1 , and wherein at least portions of the ...

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Номер записи: 85

31-07-2014 дата публикации

White light devices using non-polar or semipolar gallium containing materials and phosphors

Номер: US20140213001A1

Автор: Eric M. Hall, James W. RARING, Mark P. D'Evelyn

Принадлежит: Soraa Inc

A packaged optical device includes a substrate having a surface region with light emitting diode devices fabricated on a semipolar or nonpolar GaN substrate. The light emitting diodes emit polarized light and are characterized by an overlapped electron wave function and a hole wave function. Phosphors within the package are excited by the polarized light and, in response, emit electromagnetic radiation of a second wavelength.

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Номер записи: 86

02-05-2019 дата публикации

High Density Three-dimensional Integrated Capacitors

Номер: US20190131387A1

Автор: Haba Belgacem, Mohammed Ilyas, Oganesian Vage, Savalia Piyush

Принадлежит: TESSERA, INC.

A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates. 1. A component having electrodes for electrical interconnection with a circuit component or microelectronic element , comprising:a substrate consisting essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C., the substrate having a first surface, a second surface opposite the first surface, and an opening in the first surface having at least one dimension greater than 5 microns in a direction along the first surface, the opening extending downwardly from the first surface; and first and second electrically conductive plates connectable with respective first and second electric potentials, the first and second plates extending along an inner surface of the opening, the first and second plates being separated from one another by a dielectric layer, the first plate being grounded to the substrate; and', 'first and second electrodes, the first electrode exposed at the first surface and electrically connected to the first plate, the second electrode exposed at one of the first and second surfaces and electrically connected to the second plate., 'a capacitor, including2. A component having electrodes ...

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Номер записи: 87

26-05-2016 дата публикации

Light emitting device and method for manufacturing the same

Номер: US20160149093A1

Автор: Makoto Agatani, Masahiro Konishi, Toshio Hata

Принадлежит: Sharp Corp

By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same.

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Номер записи: 88

09-05-2019 дата публикации

Electronic device

Номер: US20190139953A1

Автор: Koji Soejima, Masaya Kawano, Yoichiro Kurita

Принадлежит: NEC Electronics Corp, Renesas Electronics Corp

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

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Номер записи: 89

28-08-2014 дата публикации

Compact Media Player

Номер: US20140240937A1

Автор: Christopher D. Prest, Claudio V. Di Leo

Принадлежит: Apple Inc

An electronic device such as a media player may be formed from electrical components such as integrated circuits, buttons, and a battery. Electrical input-output port contacts may be used to play audio and to convey digital signals. Electrical components for the device may be mounted to a substrate. The components may be encapsulated in an encapsulant and covered with an optional housing structure. The electrical input-output port contacts and portions of components such as buttons may remain uncovered by encapsulant during the encapsulation process. Integrated circuits may be entirely encapsulated with encapsulant. The integrated circuits may be packaged or unpackaged integrated circuit die. The substrate may be a printed circuit board or may be an integrated circuit to which components are directly connected without interposed printed circuit board materials.

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Номер записи: 90

25-06-2015 дата публикации

Light emitting device and method for manufacturing the same

Номер: US20150176824A1

Автор: Makoto Agatani, Masahiro Konishi, Toshio Hata

Принадлежит: Sharp Corp

By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same.

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Номер записи: 91

18-09-2014 дата публикации

Light emitting device mount, light emitting apparatus including the same, and leadframe

Номер: US20140264426A1

Автор: Ryohei Yamashita, Ryoichi Yoshimoto

Принадлежит: Nichia Corp

A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on opposing end surfaces of the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

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Номер записи: 92

02-07-2015 дата публикации

Optoelectronic system

Номер: US20150188003A1

Автор: Cheng-Nan HAN, Hsin-Mao Liu, Min-Hsun Hsieh, Steve Meng-Yuan Hong, Tsung-Xian Lee

Принадлежит: Epistar Corp

An embodiment of the invention discloses an optoelectronics system. The optoelectronic system includes an optoelectronic element having a first width; an adhesive material enclosing the optoelectronic element and having a second width larger than the first width; a phosphor structure formed between the optoelectronic element and the adhesive material; and a transparent substrate formed on the adhesive material.

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Номер записи: 93

11-06-2020 дата публикации

SEMICONDUCTOR PACKAGE INCLUDING ORGANIC INTERPOSER

Номер: US20200185296A1

Автор: Lee Dong Hun

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor package including an organic interposer includes: the organic interposer including insulating layers and wiring layers formed on the insulating layers; a stiffener disposed on the interposer and having a through-hole; a first semiconductor chip disposed in the organic through-hole on the organic interposer; a second semiconductor chips disposed adjacent to the first semiconductor chip in the through-hole on the organic interposer; and an underfill resin filling at least portions of the through-hole and fixing the first semiconductor chip and the second semiconductor chip, wherein the connection pads of the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the wiring layers of the organic interposer. 118-. (canceled)19. A semiconductor package , comprising:an organic interposer including wiring layers;a first semiconductor chip disposed on the organic interposer and electrically connected to the wiring layers of the organic interposer;a plurality of second semiconductor chips disposed adjacent to the first semiconductor chip and electrically connected to the wiring layers of the organic interposer, wherein two or more plurality of second semiconductor chips among the plurality of second semiconductor chips are adjacent to one side of the first semiconductor chip and two or more plurality of second semiconductor chips among the plurality of second semiconductor chips are adjacent to the other side opposite to the one side of the first semiconductor chip;a warpage control material disposed on the organic interposer and having a surrounding portion surrounding the first semiconductor chip and the plurality of second semiconductor chips, and a plurality of protruding portions extending from the surrounding portion to between two adjacent second semiconductor chips adjacent to the same side of the first semiconductor chip among the plurality of second semiconductor chips; andan underfill resin ...

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Номер записи: 94

14-07-2016 дата публикации

Semiconductor device

Номер: US20160204092A1

Автор: Yoichiro Kurita

Принадлежит: Renesas Electronics Corp

The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101 , an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113 , and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101 . The interconnect component 101 has a constitution where an interconnect layer 103 , a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

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Номер записи: 95

20-07-2017 дата публикации

Electrical Feedthrough Assembly

Номер: US20170203108A1

Автор: Beerling Timothy, Downing Mark B., Koester Kurt J., Palmer Logan P., Stuursma David, Thenuwara Chuladatta

Принадлежит:

A device includes a hermetically sealed case with electronic circuitry housed within. One surface of the hermetically sealed case includes a metallic plate and a co-fired ceramic electrical feedthrough with a number of vias. The co-fired ceramic electrical feedthrough is hermetically joined to the metallic plate and a hybrid circuit is connected to the feedthrough. 1. A feedthrough comprising:a body having a first side and a second side separated by a thickness;a first conductive pad on the first side;a second conductive pad on the second side; anda plurality of conductive vias electrically connecting the first conductive pad and the second conductive pad.2. The feedthrough of claim 1 , wherein the first conductive pad and second conductive pad comprise different materials.3. The feedthrough of claim 1 , wherein the first conductive pad and the second conductive pad have a common geometry.4. The feed through of claim 3 , wherein a center point of the first conductive pad and a center point of the second conductive pad could be connected by a straight line perpendicular to the first and second conductive pads.5. The feedthrough of claim 1 , wherein the vias have a common geometry.6. The feedthrough of claim 1 , wherein the vias are equidistant from each other.7. The feedthrough of claim 1 , wherein a center of a cross-section of each via is equidistant from a center-point of the first conductive pad.8. The feedthrough of claim 1 , wherein the plurality of vias comprises three vias.9. The feedthrough of claim 1 , wherein each via has a separate contact with the first conductive pad.10. The feedthrough of claim 1 , wherein each via does not electrically communicate with any other via except through the first and second conductive pads.11. The feedthrough of claim 1 , wherein a projection of each via onto the first side remains within a perimeter of the first conductive pad.12. The feedthrough of claim 1 , wherein each via is straight and extends perpendicular to the ...

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Номер записи: 96

19-07-2018 дата публикации

HIGH-FREQUENCY MODULE

Номер: US20180204781A1

Автор: OTSUBO Yoshihito

Принадлежит:

A high-frequency module la includes: a wiring substrate a plurality of components and that are mounted on an upper surface of the wiring substrate a sealing resin layer that is stacked on the upper surface of the wiring substrate a shield film that covers a surface of the sealing resin layer and a shield wall that is provided in the sealing resin layer The shield wall is formed of two shield wall element bodies and that have straight line shapes in a plan view, and the two shield wall element bodies and are arranged such that the shield wall element bodies each have one end surface that is not exposed at a different peripheral side surface of the sealing resin layer 1. A high-frequency module comprising:a wiring substrate;a plurality of components mounted on a main surface of the wiring substrate;a sealing resin layer stacked on the main surface of the wiring substrate and sealing the plurality of components; anda shield wall provided in the sealing resin layer and arranged so as to partition the sealing resin layer into a plurality of regions, wherein at least one prescribed component is respectively mounted in each of the plurality of regions;wherein the shield wall includes a plurality of shield wall element bodies, and each of the plurality of shield wall element bodies has at least one end portion not exposed at a side surface of the sealing resin layer.2. The frequency module according to claim 1 , wherein the shield wall partitions the sealing resin layer into two regions claim 1 , and wherein when one of the two regions partitioned by the shield wall is viewed from another one of the two regions claim 1 , at least a part of one of the plurality of shield wall element bodies different from another one of the plurality of shield wall element bodies is arranged in a place where the other shield wall element body is not arranged.3. The frequency module according to claim 2 ,wherein the plurality of shield wall element bodies are each arranged so as to be ...

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Номер записи: 97

06-08-2015 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20150221573A1

Автор: Paek Jong Sik, Park Doo Hyun

Принадлежит:

A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate. 1. A manufacturing method of a semiconductor device , the manufacturing method comprising:forming a back end of line (BEOL) layer on a dummy substrate;electrically connecting a semiconductor die to the BEOL layer;first encapsulating the BEOL layer and the semiconductor die using a first encapsulant;removing the dummy substrate from the BEOL layer;electrically connecting a solder ball to the BEOL layer;second encapsulating the BEOL layer and the solder ball using a second encapsulant; andelectrically connecting a semiconductor package to the BEOL layer.2. The manufacturing method of claim 1 , wherein the dummy substrate comprises one or more of: silicon claim 1 , glass claim 1 , silicon carbide claim 1 , sapphire claim 1 , quartz claim 1 , ceramic claim 1 , metal oxide and/or a metal.3. The manufacturing method of claim 1 , wherein the semiconductor package is electrically connected to the BEOL layer by at least a conductive pillar passing through the first encapsulant.4. The manufacturing method of claim 3 , comprising forming the conductive pillar by claim 3 , at least in part claim 3 , plating the conductive pillar on the BEOL layer.5. The manufacturing method of claim 3 , comprising forming the conductive pillar by claim 3 , at least in part claim 3 , bonding a wire to the BEOL layer.6. The manufacturing method of claim 3 , comprising bonding the semiconductor die to the conductive pillar using flip-chip technology.7. The manufacturing method of claim 1 , wherein the solder ball is exposed to the outside through the second encapsulant.8. The manufacturing method of claim 1 , comprising forming a redistribution layer on the first encapsulant and electrically connected to the BEOL layer claim 1 , and comprising ...

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Номер записи: 98

26-07-2018 дата публикации

PACKAGED SEMICONDUCTOR COMPONENTS HAVING SUBSTANTIALLY RIGID SUPPORT MEMBERS AND METHODS OF PACKAGING SEMICONDUCTOR COMPONENTS

Номер: US20180211896A1

Автор: Brooks J. Michael, Corisis David J., Schwab Matt E.

Принадлежит:

Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die. 1. A packaged semiconductor component , comprising:a semiconductor die having a first composition, a first surface, a bond pad located on or near the first surface, and a second surface opposite the first surface;an array of photo sensors at least partially embedded in the semiconductor die proximate to the first surface;a support member attached to the first surface of the semiconductor die, the support member being at least substantially rigid and having a second composition different from the first composition of the semiconductor die, the support member including an opening generally aligned with the bond pad located on or near the first surface;a substrate carrying the semiconductor die and the support member attached to the semiconductor die; andan encapsulant at least partially encasing the semiconductor die, the support member, and the substrate.2. The packaged semiconductor component of claim 1 , wherein the package further includes a plurality of solder balls between the first surface of the semiconductor die and the substrate claim 1 , individual solder balls electrically connecting the bond pad of the semiconductor die to the substrate.3. The packaged semiconductor component of wherein the semiconductor die is a first semiconductor die and the package further includes a second semiconductor die claim 1 , and wherein the support member is between the first and second semiconductor dies.4. The packaged semiconductor ...

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Номер записи: 99

13-08-2015 дата публикации

Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation

Номер: US20150228628A1

Автор: Byung Tai Do, Linda Pei Ee CHUA, Reza A. Pagaila

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

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Номер записи: 100