СВЕТОИЗЛУЧАЮЩИЙ ПРИБОР С ПРЕОБРАЗУЮЩИМ ДЛИНУ ВОЛНЫ БОКОВЫМ ПОКРЫТИЕМ

Полупроводниковый светоизлучающий прибор содержит первый преобразующий длину волны элемент, расположенный на верхней светоизлучающей поверхности полупроводникового светоизлучающего прибора, при этом первый преобразующий длину волны элемент содержит первый преобразующий длину волны материал, который не шире, чем эта верхняя светоизлучающая поверхность; и второй преобразующий длину волны элемент, расположенный на боковой поверхности полупроводникового светоизлучающего прибора, при этом второй преобразующий длину волны элемент содержит второй преобразующий длину волны материал, который не простирается на верхнюю светоизлучающую поверхность, при этом первый и второй преобразующие длину волны материалы являются разными преобразующими длину волны материалами. Изобретение обеспечивает повышение эффективности устройства. 2 н. и 14 з.п. ф-лы, 6 ил.

СПОСОБ И УСТАНОВКА ДЛЯ ВСКРЫТИЯ ПОВЕРХНОСТИ ИНТЕГРАЛЬНОЙ СХЕМЫ

... 1. Способ вскрытия интегральной схемы путем абляции полимерной оболочки, первоначально покрывающей интегральную схему, характеризующийся тем, что включает комбинированное воздействие лазерным лучом и плазмой на оболочку, первоначально покрывающую интегральную схему, при этом комбинирование воздействие осуществляют в одном и том же замкнутом пространстве (16). ! 2. Способ по п.1, в котором сначала выполняют этап (72) воздействия лазерным излучением, затем этап (74) воздействия плазмой. ! 3. Способ по п.2, в котором этап (74) воздействия плазмой инициируют в то время, когда на интегральную схему по-прежнему действуют лазерным излучением. ! 4. Способ по п.2 или 3, в котором лазерное излучение применяют (72) до тех пор, пока толщина остаточного полимерного слоя над интегральной схемой не составит от 50 до 200 мкм. ! 5. Способ по п.2, характеризующийся тем, что содержит две последовательные фазы обработки сначала лазерным излучением, затем плазмой. ! 6. Способ по п.2, в котором воздействие лазерным ...

РЕГУЛИРОВАНИЕ КРАЕВОГО ИЗЛУЧЕНИЯ В МАТРИЦЕ СИД, ОТДЕЛЕННОЙ ОТ БЛОКА

... 1. Способ производства структур светоизлучающих диодов (СИД) на одной пластине, включающий в себя:формирование пластины устройства с матрицами СИД;разъединение матриц СИД на пластине устройства;разделение матриц СИД с целью создания промежутков между матрицами СИД;нанесение по существу непрерывного отражающего покрытия на поверхность матриц СИД и в промежутках между матрицами СИД;удаление первых частей отражающего покрытия с поверхности матриц СИД; иразлом или отделение отражающего покрытия в промежутках между матрицами СИД,при этом вторые части отражающего покрытия остаются на боковых сторонах матриц СИД, чтобы регулировать краевое излучение.2. Способ по п.1, в котором отражающее покрытие является полимером или смолой с отражающими частицами.3. Способ по п.2, в котором отражающее покрытие является силиконом, эпоксидной смолой или акриловым материалом, а отражающие частицы являются оксидом титана, оксидом цинка, двуокисью кремния, окисью алюминия или двуокисью циркония.4. Способ по п.2, ...

Bauelement mit Begrenzungselement

Es wird ein Bauelement (10) mit einem Halbleiterchip (1), einem Gehäuse (9) und einer reflektierenden Schicht (2) angegeben, wobei das Gehäuse einen Formkörper (90) und einen Grundkörper (91) aufweist, wobei der Formkörper den Grundkörper oder eine Kavität (8) des Gehäuses lateral umschließt und verschieden von der reflektierenden Schicht ist. Der Hauptkörper weist eine in Draufsicht von dem Formkörper unbedeckte Freifläche (80A) auf. Die Freifläche oder eine Bodenfläche (80) der Kavität umfasst eine Montagefläche (81) für den Halbleiterchip, wobei der Halbleiterchip auf der Montagefläche angeordnet ist. Die Bodenfläche oder die Freifläche ist bereichsweise von der reflektierenden Schicht bedeckt, wobei die Montagefläche von einem Begrenzungselement (3) zumindest bereichsweise umschlossen ist, das an die reflektierende Schicht angrenzt und dazu eingerichtet ist, eine Bedeckung des Halbleiterchips durch die reflektierende Schicht zu verhindern.

Wafer-level packaging for a fingerprint sensor

A fingerprint sensor package 10, including a sensing side 12 for sensing fingerprint information and a separate connection side 14 for electrically connecting the fingerprint sensor package to a host device 18, is disclosed. The fingerprint sensor package also includes a sensor integrated circuit facing the sensing side and substantially surrounded by a fill material 16. The fill material can include vias (44) at peripheral locations around the sensor integrated circuit. The fingerprint sensor package can further include a redistribution layer 30 on the sensing side which redistributes connections of the sensor integrated circuit to the vias. The connections can further be directed through the vias to a ball grid array (25) on the connection side. Some aspects also include electrostatic discharge traces positioned at least partially around a perimeter of the connection side. Methods of manufacturing are also disclosed.

METHOD FOR THE SEPARATION FROM SUBSTRATES

SLIP CHIP DEVICE AND METHODS

A device is described having a first surface having a plurality of first areas and a second surface having a plurality of second areas. The first surface and the second surface are opposed to one another and can move relative to each other from at least a first position where none of the plurality of first areas, having a first substance, are exposed to plurality of second areas, having a second substance, to a second position. When in the second position, the plurality of first and second areas, and therefore the first and second substances, are exposed to one another. The device may further include a series of ducts in communication with a plurality of first second areas to allow for a substance to be disposed in, or upon, the plurality of second areas when in the first position.

Semiconductor device and a method of manufacturing the same

For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Semiconductor device and a method of manufacturing the same

COMPOUND CONTAINING PHENOLIC HYDROXYL GROUP, PHENOLIC RESIN, CURABLE COMPOSITION, CURED PRODUCT THEREOF, SEMICONDUCTOR SEALING MATERIAL, AND PRINTED CIRCUIT BOARD

METHOD FOR MANUFACTURING WIRING BOARD

Package of Semiconductor Device

디바이스 다이의 링 구조물

... 다이는 금속 패드, 금속 패드 위에 패시베이션 층 및 패시베이션 층 위에 폴리머 층을 포함한다. 금속 필라가 전기적으로 금속 패드에 위에서 연결된다. 금속 링은 상기 금속 필라와 동일 평면 상에 있다. 상기 폴리머 층은 금속 필라 및 금속 링과 동일 평면 상의 부분을 포함한다.

METHOD FOR FORMING INTERCONNECT STRUCTURE

FLEXIBLE LIGHT EMITTING SEMICONDUCTOR DEVICE

método de fabricação de dispositivo de emissão de luz

Methods of forming electronic devices

Methods of forming electronic devices are provided. The methods involve alkaline treatment of photoresist patterns and allow for the formation of high density resist patterns. The methods find particular applicability in semiconductor device manufacture.

Airgap interconnect with hood layer and method of forming

An airgap interconnect structure with hood layer and methods for forming such an airgap interconnect structure are disclosed. A substrate having a dielectric layer with a plurality of interconnects formed therein is provided. Each interconnect is encapsulated by a barrier layer. A hardmask is formed on the dielectric layer and patterned to expose the dielectric layer between adjacent interconnects where an airgap is desired. The dielectric layer is etched to form a trench, wherein the etching process additionally etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect. A hood layer is electrolessly plated onto an exposed portion of the top surface and the exposed portion of the side surface to reseal the interconnect. A gap-sealing dielectric layer is formed over the device, sealing the trench to form an airgap.

Liquid adhesive for an electronic component and adhesive tape

A liquid adhesive for an electronic component; wherein a component (a) which is an acrylonitrile-butadiene copolymer, a component (b) which is a phenolic resin, and a component (c) which is a compound having two or more maleimide groups are dissolved in an organic solvent, and the component (c) comprises a compound represented by the general formula (1) and a compound represented by the general formula (2).

Power overlay structure and method of making same

CONTROLLED-SHAPED SOLDER RESERVOIRS FOR INCREASING THE VOLUME OF SOLDER BUMPS, AND STRUCTURES FORMED THEREBY

METHOD OF FORMING SEMICONDUCTOR DEVICE

Method of forming a micro device transfer head with silicon electrode

Adhesive material, adhesive method and adherend using the asme

Managing power on integrated circuits using power islands

MARK, METHOD FOR FORMING SAME, AND EXPOSURE APPARATUS

A mark forming method includes: forming recessed portion on a mark formation area of a substrate; coating the recessed portion with a polymer layer containing a block copolymer, allowing the polymer layer in the recessed portion to form a self-assembled area; selectively removing a portion of the self-assembled area; and forming a positioning mark by using the self-assembled area from which the portion thereof has been removed.

Light emitting device package

A light emitting device package is provided. The light emitting device package may include a main body having a cavity including side surfaces and a bottom, and a first reflective cup and a second reflective cup provided in the bottom of the cavity of the main body and separated from each other. A first light emitting device may be provided in the first reflective cup, and a second light emitting device may be provided in the second reflective cup.

Vertical probe card

A probe card includes a circuit board and a probe set. The probe set is electrically coupled to the circuit board. Also, the probe set includes a plurality of probes. Each of the plurality of probes includes a plurality of nanotwinned copper pillars that are arranged in a predetermined crystal orientation. In addition, each of the plurality of probes further includes a tip. The tip substantially and electrically contacts a chip. Such that the circuit board can test the chip via the tip.

3D packaging with low-force thermocompression bonding of oxidizable materials

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression ...

Power managers for an integrated circuit

A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.

Shielded EHF connector assemblies

Shielded extremely high frequency (EHF) connector assemblies are disclosed herein. In some embodiments, a first extremely high frequency (EHF) shielded connector assembly configured to be coupled with a second EHF shielded connector assembly. The first EHF connector assembly can include a first EHF communication unit operative to contactlessly communicate EHF signals with a second EHF communication unit included in the second EHF shielded connector assembly. The first connector can include a connector interface that includes a configuration to interface with a respective connector interface of the second EHF shield connector assembly, and several different material compositions that, in conjunction with the configuration, provide shielding to prevent or substantially reduce EHF signal leakage when the first EHF assembly connector is coupled to the second EHF assembly connector and the first EHF communication unit is contactlessly communicating EHF signals with the second EHF communication ...

SGS or GSGSG pattern for signal transmitting channel, and PCB assembly, chip package using such SGS or GSGSG pattern

A substrate having multiple metal layers is disclosed. The substrate includes a plurality of metal layers disposed in different levels. The plurality of metal layers includes a lower metal layer, a middle metal layer situated overlying the lower layer, and an upper metal layer situated overlying the middle metal layer. A solder mask covers the upper metal layer. A reference plane is arranged in the lower metal layer. A trio of signal traces is arranged in the middle metal layer. The trio of signal traces comprises at least a pair of differential signal traces. A plurality of reference nets is arranged in the middle metal layer.

SWITCHED POWER STAGE WITH INTEGRATED PASSIVE COMPONENTS

A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching regulator is matched with an inductor built within an area above the switches. In some embodiments the combined switches and inductor are constructed as a unit cell and can be combined to form larger elements as required for higher current drive capability and multiphase operation.

Methods of forming electronic devices

Methods of forming electronic devices are provided. The methods involve alkaline treatment of photoresist patterns and allow for the formation of high density resist patterns. The methods find particular applicability in semiconductor device manufacture.

Integrated circuit device

The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern, and the second metal pattern. The third metal pattern is electrically grounded. An inductor is disposed over the third metal pattern.

Attachment feature removal from photomask in extreme ultraviolet lithography application

Embodiments of the present disclosure generally provide apparatus and methods for removing an attachment feature utilized to hold a pellicle from a photomask. In one embodiment, an attachment feature removal apparatus for processing a photomask includes an attachment feature puller comprising an actuator, a clamp coupled to the actuator, the clamp adapted to grip an attachment feature, and a coil assembly disposed adjacent to the attachment feature.

SOLID-STATE IMAGING APPARATUS

A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member.

PREGREG, FILM WITH RESIN, METAL FOIL WITH RESIN, METAL-CLAD LAMINATE, AND PRINTED WIRING BOARD

The present invention provides the prepreg being formed by impregnating a fiber base material with a resin composition and the resin composition comprising an acrylic resin, wherein the ratio of the peak height near 2240 cm−1 due to nitrile groups (PCN) with respect to the peak height near 1730 cm−1 due to carbonyl groups (PCO) in the IR spectrum of the cured resin composition (PCN/PCO) is no greater than 0.001 and the like in order to provide a prepreg, a film with a resin, a metal foil with a resin and a metal-clad laminate, which exhibit excellent bending resistance while also prevent ion migration and have excellent insulating reliability when printed wiring boards are fabricated, as well as a printed wiring board employing the same.

Packaged Overvoltage Protection Circuit For Triggering Thyristors

In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.

Chip diode and diode package

... [Theme] To provide a chip diode, with which a p-n junction formed on a semiconductor layer can be prevented from being destroyed and fluctuations in characteristics can be suppressed even when a large stress is applied to a pad for electrical connection with the exterior, and a diode package that includes the chip diode. [Solution] A chip diode 15 includes an epitaxial layer 21 with a p-n junction 28, constituting a diode element 29, formed therein, an anode electrode 34 disposed along a top surface 22 of the epitaxial layer 21, electrically connected to a diode impurity region 23, which is the p-side pole of the p-n junction 28, and having a pad 37 for electrical connection with the exterior, and a cathode electrode 41 electrically connected to the epitaxial layer 21, which is the n-side pole of the p-n junction 28, and the pad 37 is provided at a position separated from a position directly above the p-n junction 28.

Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby

A controlled-shaped solder reservoir (32) provides additional solder to a bump (36) in the flow step for increasing the volume of solder forming the solder bump (36). The controlled shaped reservoirs (32) can be shaped and sized to provide predetermined amounts of solder to the solder bump (36). Thus, the height of the resulting solder bump can be predetermined. The solder reservoirs (32) can be shaped to take a minimum amount of space, such as by at least partially wrapping around the solder bump. Consequently, the solder bumps may have increased height without adding to the space requirements of the solder bump, or without increasing the fabrication cost. In addition, due to the finite time required for solder flow, a means of sequencing events during soldering is provided.

Lotlegierungen und Anordnungen

Eine Lotlegierung wird bereitgestellt, wobei die Lotlegierung Zink, Aluminium, Magnesium und Gallium aufweist, wobei das Aluminium bezogen auf das Gewicht 8% bis 20% der Legierung ausmacht, das Magnesium bezogen auf das Gewicht 0,5% bis 20% der Legierung ausmacht und das Gallium bezogen auf das Gewicht 0,5 bis 20% der Legierung ausmacht und der Rest der Legierung Zink aufweist.

Chipkartenmodul

In verschiedenen Gesichtspunkten der Offenbarung wird ein Chipkartenmodul (100) bereitgestellt. Das Chipkartenmodul (100) kann ein flexibles Substrat (106) mit einer Metallisierung auf einer ersten und einer zweiten Hauptoberfläche oder einer Seite davon beinhalten. Eine integrierte Schaltung (102), die an die zweite Seite befestigt ist, ist mit Chip-Pads (114) ausgerichtet, die von dem Substrat (106) abgewandt sind. Drahtbonds (110) können die Chip-Pads (114) mit der zweiten Metallisierung verbinden.

Rührreibschweißstruktur und Leistungshalbleitervorrichtung

Eine Rührreibschweißstruktur besteht aus einem ersten und einem zweiten Element, die durch Rührreibschweißen zu einem Stück verbunden werden, wobei ein dünner Abschnitt entlang dem Rührreibschweißabschnitt an entweder dem ersten oder dem zweiten Element oder an beiden gebildet ist.

SLIP CHIP DEVICE AND METHODS

A device is described having a first surface having a plurality of first areas and a second surface having a plurality of second areas. The first surface and the second surface are opposed to one another and can move relative to each other from at least a first position where none of the plurality of first areas, having a first substance, are exposed to plurality of second areas, having a second substance, to a second position. When in the second position, the plurality of first and second areas, and therefore the first and second substances, are exposed to one another. The device may further include a series of ducts in communication with a plurality of first second areas to allow for a substance to be disposed in, or upon, the plurality of second areas when in the first position.

COVER MEMBER FOR A ROBOT USED IN A PAINTING PROCESS HAVING ABSORPTIVE PROPERTIES

A cover member for a robot used in a painting process includes an inner knitted substructure, an outer knitted substructure and a spacer yarn positioned between and secured to the inner and outer knitted substructures. The cover member has stretchability, compressibility and resiliency similar to conventional resilient foam materials while at the same time providing characteristics for absorbing paint to substantially reduce paint dripping.

Substrate dividing method

WIRING STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor package and method for manufacturing the same

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die (s) bonded to the interposer die can have edge (s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.

Light emitting device, resin package, resin compact and method of manufacturing the same

Provided is an easy and inexpensive method of manufacturing a large number of light emitting devices having high adhesion between a lead frame and a thermosetting resin composition in a short period of time. A method of manufacturing a light emitting device having a resin package 20 with optical reflectance of 70% or more at a wavelength of 350 nm to 800 nm after thermally set and in which a resin portion 25 and leads 22 are formed on approximately the same plane at a side surface 20b, the method includes the steps of interposing a lead frame 21 having cutouts 21a formed therein between an upper mold 61 and a lower mold 62, forming a resin compact 24 on the lead frame 21 by transfer molding a thermosetting resin 23 including an optical reflective material 26 into the cavity of the mold 60 formed between the upper mold 61 and the lower mold 62, and cutting the resin compact 24 and the lead frame 21 along the cutouts 21a.

Light-emitting device

A light-emitting device comprising: a light-emitting stack layer with a length and a width comprising: a first conductivity type semiconductor layer; an active layer on the first conductivity type semiconductor layer; and a second conductivity type semiconductor layer on the active layer; a conductive layer with a width greater than the width of the first conductivity type semiconductor layer under the first conductivity type semiconductor layer, the conductive layer comprising a first overlapping part which overlaps the first conductivity type semiconductor layer, and a first extending part which does not overlap the first conductivity type semiconductor layer; a transparent conductive layer with a width greater than the width of the second conductivity type semiconductor layer over the second conductivity type semiconductor layer, the transparent conductive layer comprising a second overlapping part which overlaps the second conductivity type semiconductor layer, and a second extending ...

Substrate dividing method

A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.

Crack stop barrier and method of manufacturing thereof

A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip. The kerf comprises a crack stop barrier.

CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

Method of manufacturing cu core ball

A Cu core ball and a method of manufacturing such a Cu core ball. Purity of the Cu internal ball is at least 99.9% and not greater than 99.995%. A total contained amount of Pb and/or Bi in impurity contained in the Cu ball is equal to or larger than 1 ppm. Its sphericity is at least 0.95. A solder plating film coated on the Cu ball is of Sn solder or a lead free solder alloy whose primary component is Sn. In the solder plating film, a contained amount of U is not more than 5 ppb and that of Th is not more than 5 ppb. A total alpha dose of the Cu ball and the solder plating film is not more than 0./0200 cph/cm2. An arithmetic average roughness of the Cu core ball is equal to or less than 0.3 μm.

Controlling warping in integrated circuit devices

Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Semiconductor package and manufacturing method of the same

The present disclosure provides a semiconductor package, including a first semiconductor die layer having an active surface, a conductive contact electrically coupled to the active surface, a sidewall of the conductive contact being surrounded by an insulating layer, and a solder bump connected to the conductive contact. A seed layer is between the sidewall of the conductive contact and the insulating layer. The present disclosure provides a method for manufacturing a semiconductor package, the method including providing a carrier, forming an insulating layer over the carrier, debonding the carrier from the insulating layer, and exposing the conductive contact from the insulating layer by an etching operation.

GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION

Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Porous semiconductor handle substrate

An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Method for forming solder deposits

A method for forming solder deposits on elevated contact metallizations of terminal faces of a substrate formed in particular as a semiconductor component includes bringing wetting surfaces of the contact metallizations into physical contact with a solder material layer. The solder material is arranged on a solder material carrier. At least for the duration of the physical contact, a heating of the substrate and a tempering of the solder material layer takes place. Subsequently a separation of the physical contact between the contact metallizations wetted with solder material and the solder material layer takes place.

Field-effect transistor, display element, image display device, and system

A field-effect transistor including: a gate electrode; a source electrode and a drain electrode; an active layer disposed to be adjacent to the source electrode and the drain electrode and including a n-type oxide semiconductor; and a gate insulating layer disposed between the gate electrode and the active layer, wherein the n-type oxide semiconductor undergoes substitutional doping with at least one dopant selected from divalent, trivalent, tetravalent, pentavalent, hexavalent, heptavalent, and octavalent cations, valence of the dopant is greater than valence of a metal ion constituting the n-type oxide semiconductor, provided that the dopant is excluded from the metal ion, and the source electrode and the drain electrode include a material selected from Au, Pt, and Pd and alloys including at least any one of Au, Pt, and Pd, in at least contact regions of the source electrode and the drain electrode with the active layer.

Identification circuit and IC chip comprising the same

An embodiment of the present invention is an identification circuit for generating an identification number (ID). The identification circuit includes a plurality of identification cells each comprising a latch having a first output and a second output that are opposite to each other. The first output and the second output are a function of process variations of the identification circuit. A first buffer and a second buffer are provided on both sides of the latch and connected to the first output and the second output of the latch, respectively.

LIGHT EMITTING DEVICE, RESIN PACKAGE, RESIN-MOLDED BODY, AND METHODS FOR MANUFACTURING LIGHT EMITTING DEVICE, RESIN PACKAGE AND RESIN-MOLDED BODY

A method of manufacturing a light emitting device having a resin package which provides an optical reflectivity equal to or more than 70% at a wavelength between 350 nm and 800 nm after thermal curing, and in which a resin part and a lead are formed in a substantially same plane in an outer side surface, includes a step of sandwiching a lead frame provided with a notch part, by means or an upper mold and a lower mold, a step of transfer-molding a thermosetting resin containing a light reflecting material in a mold sandwiched by the upper mold and the lower mold to form a resin-molded body in the lead frame and a step of cutting the resin-molded body and the lead frame along the notch part.

Cold plate with combined inclined impingement and ribbed channels

Methods for making heat transfer devices include forming a jet plate with a plurality of inclined jets set at an angular deviation from normal. A bottom plate is formed with channel walls that have ribs. The jet plate is attached to the bottom plate to form ribbed channels. The angular deviation of each inclined jet establishes a jet direction perpendicular to a long dimension of the ribbed channels.

Methods for selecting integrated circuit dies based on pre-determined criteria

Methods for selecting integrated circuit dies based on pre-determined criteria are disclosed. A disclosed method includes binning tools that characterizes multiple integrated circuit dies based on performance attributes. Each integrated circuit die is labeled with an identifier that represents bin location of the integrated circuit die within a die storage structure. A user can search for integrated circuit dies that matches certain performance grading by providing a performance description to an input interface on testing equipment. A tester is then configured to perform a screening to identify the physical locations of integrated circuit dies that match the retrieved identifiers from the die storage structure.

Semiconductor Package and Method of Forming the Same

A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder.

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Systems and methods for single-molecule nucleic-acid assay platforms

Integrated circuits for a single-molecule nucleic-acid assay platform, and methods for making such circuits are disclosed. In one example, a method includes transferring one or more carbon nanotubes to a complementary metal-oxide semiconductor (CMOS) substrate, and forming a pair of post-processed electrodes on the substrate proximate opposing ends of the one or more carbon nanotubes.

Flexible TFT substrate having a plurality of grooves in organic material

The invention provides a flexible TFT substrate and manufacturing method thereof. The method forms a flexible base and a first organic layer on rigid substrate and forms a plurality of grooves, manufactures TFT devices in the grooves and forms a second organic layer on the first organic layer, finally peels the flexible base from the rigid substrate to obtain a flexible TFT substrate, wherein because a plurality of grooves is disposed in the first organic layer, a plurality of recessed structures and raised structures are formed on the first organic layer so that the second organic layer and the first organic layer are engaged with each other and bonded tightly, and protects the TFT devices sandwiched between the two to prevent the breaking wires, TFT peeling, and leaking light in the bending process, to enhance the flexible TFT substrate quality to prolong the lifespan of flexible TFT substrate.

СИД-МОДУЛЬ С ПРЕОБРАЗОВАНИЕМ ЛЮМИНОФОРОМ С УЛУЧШЕННЫМИ ПЕРЕДАЧЕЙ БЕЛОГО ЦВЕТА И ЭФФЕКТИВНОСТЬЮ ПРЕОБРАЗОВАНИЯ

Изобретение может быть использовано для получения белого света в осветительных устройствах. Осветительное устройство (100) содержит первый твердотельный источник (10) света, выполненный с возможностью подачи УФ-излучения (11) с длиной волны 380-420 нм; второй твердотельный источник (20) света, выполненный с возможностью подачи синего света (21) с длиной волны 440-470 нм; преобразующий длину волны элемент (200), содержащий первый люминесцентный материал (210) и второй люминесцентный материал (220). Первый люминесцентный материал (210) излучает зеленый или желтый свет (211), а второй люминесцентный материал (220) излучает оранжевый или красный свет (221), в результате чего получают белый свет (201). Преобразующий длину волны элемент (200) расположен на ненулевом расстоянии (d) от твердотельных источников света (10, 20) и выполнен в виде окна смесительной камеры (120). Осветительное устройство (100) не содержит рассеивающего элемента, но дополнительно содержит регулятор твердотельных источников ...

Verfahren für die Ausbildung einer Verbindungsstruktur

Ein Verfahren für die Ausbildung von Verbindungsstrukturen weist das Ausbilden einer Metallleitung, die aus einem ersten leitfähigen Material besteht, über einem Substrat auf, sowie das Abscheiden einer dielektrischen Schicht über der Metallleitung, das Strukturieren der dielektrischen Schicht, um eine Öffnung auszubilden, das Abscheiden einer ersten Sperrschicht auf einer Unterseite sowie auf Seitenwänden der Öffnung unter Verwendung eines atomaren Schichtabscheidungsverfahrens, das Abscheiden einer zweiten Sperrschicht über der ersten Sperrschicht, wobei die erste Sperrschicht mit Erde verbunden ist, sowie das Ausbilden eines Pads, das aus einem zweiten leitfähigen Material besteht, in der Öffnung.

Halbleiterbauteil mit oberflächenmontierbaren Außenkontakten und Verfahren zur Herstellung desselben

Die Erfindung betrifft ein Halbleiterbauteil (1) mit oberflächenmontierbaren Außenkontakten (5) auf einer Unterseite (6) des Halbleiterbauteils (1), wobei die Außenkontakte (5) auf Außenkontaktflächen (7) angeordnet und von einer Lötstopplackschicht (8) umgeben sind. Die Außenkontakte der äußeren Randbereiche (9, 11) weisen Außenkontaktflächen (13) auf, die in Kontrollfahnen (14) übergehen, und wobei die Kontrollfahnen (14) von Lotmaterial benetzbar und nicht von der Lötstopplackschicht (8) bedeckt sind.

Verfahren und Vorrichtung zur Ausbildung von Lotdepots

Verfahren zur Ausbildung von Lotdepots (34) auf erhöhten Kontaktmetallisierungen (24) von Anschlussflächen (23) eines insbesondere als Halbleiterbauelement ausgebildeten Substrats (19), bei dem Benetzungsoberflächen (26) der Kontaktmetallisierungen in Berührungskontakt mit einer auf einem Lotmaterialträger (13) angeordneten Lotmaterialschicht (15) gebracht werden, zumindest während der Dauer des Berührungskontakts eine Beheizung des Substrats und eine Temperierung der Lotmaterialschicht erfolgt, und nachfolgend eine Trennung des Berührungskontakts zwischen den mit Lotmaterial benetzten Kontaktmetallisierungen und der Lotmaterialschicht erfolgt.

Verfahren zur Herstellung eines Leistungsmoduls

Verfahren zur Herstellung eines Leistungsmoduls aufweisend folgende Schritte: • Ausbilden eines Leistungsmodul-Vorprodukts (Y) mit einem Mehrschichtsubstratkörper (X) enthaltend eine Wärmeschutzplatte (2), deren eine Fläche mit einer Fläche eines isolierenden Substrats (1) verbunden ist und die flächenmäßig kleiner ist als das isolierende Substrat (1), und ein Leistungsmodulsubstrat (3), welches mit der anderen Fläche des isolierenden Substrats (1) verbunden und mit einem Leitungsmuster ausgebildet ist, einem auf dem Leitungsmuster des Leistungsmodulsubstrats (3) angeordneten Leistungshalbleiterelement (4), einem Paar von äußeren Anschlüssen (5, 6), die in einem in orthogonaler Richtung zur Substratfläche des Leistungsmodulsubstrats (3) hochstehenden Zustand angeordnet und mit dem Leistungshalbleiterelement (4) elektrisch verbunden sind, und einem Hilfs-Harzsubstrat (9), das zwischen nach außen freiliegenden Endabschnitten des Paares von externen Anschlüssen (5, 6) und Substratverbindungsendabschnitten ...

Verfahren zur Herstellung eines Leistungsmoduls

Improved LED array

Improved LED array

Monitoring accesses to a region of an integrated circuit chip

Removing effects of instabilities of measurement system

The effects of instability of a measurement system, such as a vector network analyzer (VNA), are removed while measuring an S parameter of a device under test (DUT). A characteristic of the measurement system is initially determined, including identifying a location of an instability in the time domain; a change of the characteristic while connected to the DUT is determined; and the determined change of the characteristic is corrected by removing effects of the determined change on measurements of the S parameter of the DUT. The instability may be located in the time domain and a gated response over a gating time span may be measured in the frequency domain as the initial characteristic. The initial or factory calibration may be used to identify the location of the instability.

IMPROVED LED ARRAY

PROCEDURE FOR ISOLATING A SUBSTRATE

METHOD FOR DICING SUBSTRATE

HERMETICALLY SEALED PACKAGE HAVING STRESS REDUCING LAYER

A sealed package having a device 102 disposed on a wafer structure and a lid structure 108 bonded to the device wafer. The device wafer includes: a substrate 104; a metal ring 107DW disposed on a surface portion of substrate around the device and a bonding material 118 disposed on the metal ring. A first layer of the metal ring includes a stress relief buffer layer 109DW having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

HERMETICALLY SEALED PACKAGE HAVING STRESS REDUCING LAYER

A sealed package having a device 102 disposed on a wafer structure and a lid structure 108 bonded to the device wafer. The device wafer includes: a substrate 104; a metal ring 107DW disposed on a surface portion of substrate around the device and a bonding material 118 disposed on the metal ring. A first layer of the metal ring includes a stress relief buffer layer 109DW having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Contains the semiconductor chip of the device and method of producing such a device

Electronic circuit device

Provided is an electronic circuit device in which the bonding state of electrodes can be detected easily with high precision. The electronic circuit device has a stack structure in which a plurality of electronic circuit boards (1a, 1b, 100a, 100b, 100c) are stacked in three or more layers through ball electrodes (10a, 10b, 20a, 20b) bonded to electrode pads (30a, 30b, 40b, 50a, 60a), wherein theelectrode pads are disposed such that transmission shaded images of a pair of the electrode pads provided between adjacent layers partially overlap each other and have a non-overlapping region in which the transmission shaded images of the pair of electrode pads are free from overlapping and such that the transmission shaded image of the non-overlapping region is at least partially free from overlapping with transmission shaded images of all the other electrode pads.

OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR ADAPTING A CONTACT STRUCTURE FOR ELECTRICALLY CONTACTING AN OPTOELECTRONIC SEMICONDUCTOR CHIP

페놀 수지, 상기 페놀 수지를 포함하는 에폭시 수지 조성물, 상기 에폭시 수지 조성물의 경화물, 및 상기 경화물을 가지는 반도체 장치

... 일반식(1)로 나타내는 페놀 수지로서, 상기 페놀 수지와, 일반식(2)로 나타내는 에폭시 수지와, 경화 촉진제로부터 얻어지는 경화물에 40℃ 이상 180℃ 이하에서 1.5% 이상의 열팽창률을 부여하는 것이다. 상기 페놀 수지는, 바람직하게는, 경화물에 250℃에서 15㎫ 이상의 저장 탄성률을 부여하는 것이다.

Semiconductor package and method of making the same

Process for the formation of a silver back electrode of a passivated emitter and rear contact silicon solar cell

A process for the formation of an electrically conductive silver back electrode of a PERC silicon solar cell comprising the steps: (1) providing a silicon wafer having an ARC layer on its front-side and a perforated dielectric passivation layer on its back-side, (2) applying and drying a silver paste to form a silver back electrode pattern on the perforated dielectric passivation layer on the back-side of the silicon wafer, and (3) firing the dried silver paste, whereby the wafer reaches a peak temperature of 700 to 900 DEG C, wherein the silver paste has no or only poor fire-through capability and comprises particulate silver and an organic vehicle.

Integrated circuit package and phisical layer interface arrangement

A integrated circuit package includes a integrated circuit chip and a package carrier. The integrated circuit chip includes a substrate and a integrated circuit disposed on a active surface of the substrate. The integrated circuit includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads respectively. The second bump pads are a mirror image of the first bump pads with respect to a first geometric plane vertical to the active surface. The second inner pads are a mirror image of the first inner pads with respect to the first geometric plane.

Thermal management for light-emitting diodes

Embodiments of the invention provide lighting systems that employ light-emitting diode (LED) chips as active lighting elements. Heat management components for the LED chips employed in the lighting sources are provided. In embodiments of the invention, LED chips are cooled by one or more heatspreaders and heat sinks attached to a substrate that houses the LED chip and/or the topside of the LED chip.

Positive-type photosensitive resin composition, method for production of resist pattern, semiconductor device, and electronic device

Disclosed is a positive-type photosensitive resin composition comprising (A) a phenolic resin modified with a compound having an unsaturated hydrocarbon group and having 4 to 100 carbon atoms, (B) a compound capable of generating an acid upon being irradiated with light, (C) a thermal crosslinking agent, and (D) a solvent. The positive-type photosensitive resin composition can be developed with an aqueous alkali solution, and which enables to form a resist pattern having excellent adhesiveness and good thermal impact resistance with a sufficiently high degree of sensitivity and at a high resolution.

Wafer level package with TSV-less interposer

A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.

Application of reduced dark current photodetector with a thermoelectric cooler

A IDCA system combining thermo-electric cooler (TEC) and an internal nBn photo-detector having a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; and a contact layer comprising a doped semiconductor. A barrier layer is disposed between the photo absorbing layer and the contact layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers from the photo absorbing layer to the contact area and block the flow of thermalized majority carriers from the photo absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, and conductance band energy levels of the barrier and photo absorbing layers are equalized.

METHOD AND APPARATUS FOR REDUCING ACOUSTIC NOISE IN A SYNTHETIC JET

A synthetic jet includes a first backer structure and a first actuator coupled to the first backer structure to form a first composite unit. The synthetic jet also includes a second backer structure, and a second actuator coupled to the second backer structure to form a second composite unit. A wall member is coupled to and positioned between the first and second backer structures to form a cavity. The first composite unit has an orifice formed therethrough and the orifice is fluidically coupled to the cavity and fluidically coupled to an environment external to the cavity.

MAGNETIC SENSOR TESTING DEVICE

... [Solving Means] A magnetic sensor testing device includes electromagnets 50 and 60 that apply a magnetic field to a magnetic sensor, temperature regulators 30 and 40 that regulate a temperature of the magnetic sensor by locally applying heat to the magnetic sensor, and a controller that controls the electromagnets 50 and 60 and the temperature regulators 30 and 40, in which the controller tests the magnetic sensor in a state in which the magnetic field is applied to the magnetic sensor by the electromagnets 50 and 60 while the heat is applied to the magnetic sensor by the temperature regulators 30 and 40.

Led chip package structure

A LED chip package structure includes a substrate unit, a light-emitting unit, and a package unit. The substrate unit includes a strip substrate body. The light-emitting unit includes a plurality of LED chips disposed on the strip substrate body and electrically connected to the strip substrate body. The package unit includes a strip package colloid body disposed on the strip substrate body to cover the LED chips, wherein the strip package colloid body has an exposed top surface and an exposed surrounding peripheral surface connected between the exposed top surface and the strip substrate body, and the strip package colloid body has at least one exposed lens portion projected upwardly from the exposed top surface thereof and corresponding to the LED chips. Hence, light beams generated by the LED chips pass through the strip package colloid body to form a strip light-emitting area on the strip package colloid body.

Optoelectronic Semiconductor Component and Display Means

In at least one embodiment, an optoelectronic semiconductor component includes at least two optoelectronic semiconductor chips, which are designed to emit electromagnetic radiation in mutually different wavelength ranges when in operation. The semiconductor chips are mounted on a mounting surface of a common carrier. Furthermore, the optoelectronic semiconductor component contains at least two non-rotationally symmetrical lens bodies, which are designed to shape the radiation into mutually different emission angles in two mutually orthogonal directions parallel to the mounting surface. One of the lens bodies is here associated with or arranged downstream of each of the semiconductor chips in an emission direction.

Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Driving circuit and liquid crystal display device including the same

A tape carrier package (TCP) includes a film, a plurality of output leads and a plurality of input leads on the film, the plurality of output leads and the plurality of input leads being disposed on different sides, first and second TCP alignment marks arranged on opposing sides of the plurality of output leads, and a third TCP alignment mark at a central portion of the plurality of output leads.

Copper interconnection structure and method for forming copper interconnections

A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2.

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Clathrate, curing agent, cure accelerator, epoxy resin composition, and epoxy resin composition for encapsulation of semiconductor

It is an object of the present invention to provide a clathrate that suppresses a curing reaction at low temperature to promote an improvement in storage stability (one-component stability), and can effectively cure a resin by heating treatment. A clathrate suitable for the clathrate is a clathrate containing (b1) at least one selected from the group consisting of an aliphatic polyvalent carboxylic acid, 5-nitroisophthalic acid, 5-tert-butylisophthalic acid, 5-hydroxyisophthalic acid, isophthalic acid, and benzophenone-4,4′-dicarboxylic acid; and (b2) at least one selected from the group consisting of an imidazole compound represented by the following formula (I), and 1,8-diazabicyclo[5.4.0]undecene-7, at a molar ratio of 1:1.

Nanofluids for Thermal Management Systems

A nanofluid is generally provided for use in a heat transfer system. The nanofluid can include nanoparticles suspended in a base liquid at a nanoparticle concentration in the nanofluid of about 0.01% to about 5% by volume. The nanoparticles can include zinc-oxide nanoparticles. The nanofluid for use in a heat transfer system can, in one embodiment, further include a surfactant. Thermal management systems configured to cool a computer having integrated circuits that generate heat during use are also provided. The thermal management system can include a zinc-oxide nanofluid circulated through a series of tubes via a pump such that heat produced by electronic components of the computer can be captured by the circulating nanofluid and then removed from the nanofluid by a radiator.

Illumination device with remote luminescent material

The invention provides an illumination device comprising a light source and a transmissive arrangement. The light source is arranged to generate light source light and comprises a light emitting device (LED), arranged to generate LED light and a carrier comprising a first luminescent material. The carrier is in contact with the LED and the first luminescent material is arranged to convert at least part of the LED light into first luminescent material light. The transmissive arrangement of a second luminescent material is arranged remote from the light source and is arranged to convert at least part of the LED light or at least part of the first luminescent material light and/or at least part of the LED light. The invention overcomes current limitations of remote luminescent material systems in spot lighting. In addition, an extremely simple way of realizing light sources with various correlated colour temperatures is allowed, based on just a single type of white (or whitish) light source in combination with various (red-orange) remote luminescent materials.

Semiconductor device structures including damascene trenches with conductive structures and related method

A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.

Semiconductor chip and method for fabricating the same

A semiconductor chip includes: a semiconductor substrate in which a bonding pad is provided on a first surface thereof; a through silicon via (TSV) group including a plurality of TSVs connected to the bonding pad and exposed to a second surface opposite to the first surface of the semiconductor substrate; and a fuse box including a plurality of fuses connected to the plurality of TSVs and formed on the first surface of the semiconductor substrate.

Method for Reducing Chip Warpage

A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

System-in-a-package based flash memory card

A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Semiconductor device and package

A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO 2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO 2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

Resin-Encapsulated Semiconductor Device

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

Method of fabricating light emitting device

A method of fabricating a light emitting device includes forming a plurality of light emitting elements on light emitting element mounting regions, respectively, of a substrate, forming lens supports on the light emitting element mounting regions, respectively, are raised relative to isolation regions of the substrate located between neighboring ones of the light emitting element mounting regions, and forming lenses covering the light emitting elements on the lens support patterns, respectively.

Solid-state imaging device and method of manufacturing the same, radiological imaging apparatus and method of manufacturing the same, and method of testing solid-state imaging device

A solid-state imaging device according to one embodiment includes a plurality of signal output units. Each of the plurality of signal output units includes a first input terminal electrode group that includes a plurality of terminal electrodes for inputting a reset signal, a hold signal, a horizontal start signal, and a horizontal clock signal and a first output terminal electrode that provides output signals. The solid-state imaging device further includes a second input terminal electrode group that includes a plurality of terminal electrodes for receiving the reset signal, the hold signal, the horizontal start signal, and the horizontal clock signal, a plurality of switches that switch an electrode group which is connected with integrating circuits, holding circuits, and a horizontal shift register between the first input terminal electrode group and the second input terminal electrode group, and a second output terminal electrode.

interconnection structure for n/p metal gates

The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.

Methods of forming semiconductor chip underfill anchors

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device

The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.

Stacked semiconductor package and method of fabricating the same

A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another

A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.

Thermal siphon structure

A thermal siphon structure includes a main body, a chamber disposed therein, an evaporation section, a condensation section and a connection section positioned between the evaporation section and condensation section. The evaporation section and condensation section are respectively arranged in the chamber on two sides thereof. The connection section has a set of first communication holes and a set of second communication holes in communication with the evaporation section and condensation section. The evaporation section and condensation section respectively have multiple first and second flow guide bodies, which are arranged at intervals to define therebetween first and second flow ways. Each of the first and second flow ways has a narrower end and a wider end. The first flow ways communicate with a free area. The condensation section is designed with a low-pressure end to create a pressure gradient for driving a working fluid to circulate without any capillary structure.

Heat-dissipating assembly

A heat-dissipating assembly includes a body and a bottom plate. The body has a heat-absorbing portion. The interior of the heat-absorbing portion is provided with a chamber covered by the bottom plate. The chamber has an evaporating region for generating a high pressure, and a condensing region for generating a low pressure. The pressure gradient between the evaporating region and the condensing region is used to drive the circulation of liquid/vapor phase of a working fluid. With this structure, heat can be conducted rapidly without providing any wick structure.

Ceramic electronic component and wiring board

A ceramic electronic component includes a ceramic element body having a substantially rectangular parallelepiped shape, and first and second external electrodes. The first and second external electrodes are provided on a first principal surface. Portions of the first and second external electrodes project further than the other portions in a thickness direction. A projecting portion of the first external electrode is provided at one end of the first external electrode in a length direction and a second projecting portion of the second external electrode is provided at another end of the second external electrode in the length direction. Thus, a concave portion is provided between the projecting portions, and a portion of the first principal surface provided between the first and second external electrodes is exposed.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a SiC substrate, a semiconductor layer formed on the SiC substrate, a via hole penetrating through the SiC substrate and the semiconductor layer, a Cu pad that is formed on the semiconductor layer and is in contact with the via hole, and a barrier layer covering an upper face and side faces of the Cu pad, and restrains Cu diffusion.

Integrated lighting apparatus and method of manufacturing the same

An integrated lighting apparatus includes at least a lighting device, a control device comprising an integrated circuit, and a connector that is used to electrically connect the lighting device and the control device. With the combination, the integrated circuit drives the lighting device in accordance with its various designed functionality, thus expands applications of the integrated lighting apparatus.

Electrostatic discharge protection device and method for fabricating the same

The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.

Switching element, variable inductor, and electronic circuit device having circuit configuration incorporating the switching element and the variable inductor

An inexpensive variable inductor has inductance value continuously changeable without reducing a Q value. When a control voltage is applied to a control terminal of a MOS transistor from a power supply, a continuity region is formed in a channel, and a region between main terminals becomes conductive. When the control voltage is changed, length of the continuity region in the channel is changed. This changes length of a path area of an induced current, flowing in an induced current film. Thus, the amount of induced current is increased or decreased. Therefore, when the control voltage of the MOS transistor is changed, the inductance value of the coil is continuously changed.

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

Methods of forming semiconductor elements using micro-abrasive particle stream

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

In-line metrology system

A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.

Method of fabricating film circuit substrate and method of fabricating chip package including the same

A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area.

Array configuration and readout scheme

The described embodiments may provide a chemical detection circuit that may comprise a plurality of first output circuits at a first side and a plurality of second output circuits at a second side of the chemical detection circuit. The chemical detection circuit may further comprise a plurality of tiles of pixels each placed between respective pairs of first and second output circuits. Each tile may include four quadrants of pixels. Each quadrant may have columns with designated first columns interleaved with second columns. Each first column may be coupled to a respective first output circuit in first and second quadrants, and to a respective second output circuit in third and fourth quadrants. Each second column may be coupled to a respective second output circuit in first and second quadrants, and to a respective first output circuit in third and fourth quadrants.

Semiconductor device and method of manufacturing semiconductor device

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

Integrated circuit combination of a target integrated circuit and a plurality of cells connected thereto using the top conductive layer

A target integrated circuit (TIC) having a top conductive layer (TCL) that may be connected to a plurality of cells that are further integrated over the TIC. Each of the plurality of cells comprises two conductive layers, a lower conductive layer (LCL) below the cell and an upper conductive layer (UCL) above the cell. Both conductive layers may connect to the TCL of the TIC to form a super IC structure combined of the TIC and the plurality of cells connected thereto. Accordingly, conductivity between the TIC as well as auxiliary circuitry to the TIC maybe achieved.

Semiconductor device and semiconductor package including the same

Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.

Leadframe for ic package and method of manufacture

A leadframe for use in an integrated circuit (IC) package comprising a metal strip partially etched on a first side. In some embodiments, the leadframe may be selectively plated on the first side and/or on a second side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of electrical contacts to be electrically coupled to the leadframe and the IC chip.

Semiconductor device and method of designing a wiring of a semiconductor device

A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.

Chip package and fabricating method thereof

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO 2 skeleton; a second porous layer that is formed immediately above the first porous layer and includes a SiO 2 skeleton; a via wiring that is provided in the first porous layer; and a trench wiring that is buried in the second porous layer. The first porous layer has a pore density x 1 of 40% or below and the second porous layer has a pore density x 2 of (x 1 +5) % or above.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

Color-temperature-tunable device

A color-temperature-tunable device comprises a first light emitting diode (LED) chip group comprising at least one first blue LED chip that emits a first light having a first peak wavelength, a second LED chip group comprising at least one second blue LED chip that emits a second light having a second peak wavelength different from the first peak wavelength, and a wavelength converting layer above at least a portion of the first LED chip group and a portion of the second LED chip group. The first LED chip group and the second LED chip group are driven by a first driving current and a second driving current, respectively.

Battery heating circuits and methods using resonance components in series based on current limiting and voltage inversion with bi-directionality and common inductance

Certain embodiments of the present invention provide a battery heating circuit, wherein: a battery E, a damping component R 1 , a current storage component L 1 , a switch unit DK 1 and a charge storage component C 1 are connected in series to form a battery discharging circuit; a current storage component L 2 is connected with a one-way semiconductor component D 3 in series, and then the series circuit composed of the current storage component L 2 and the one-way semiconductor component D 3 is connected in parallel to the ends of the switch unit DK 1 ; the charge storage component C 1 , the current storage component L 2 and the one-way semiconductor component D 3 are connected in series in sequence to form a battery back-charging circuit; and a switch unit DK 2 is connected in parallel to the ends of the serially connected charge storage component C 1 and current storage component L 2.

Semiconductor device having switching element and free wheel diode and method for controlling the same

A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Electronics substrate with enhanced direct bonded metal

A substrate for electronic components includes a ceramic tile and a cooling metal layer. The cooling metal layer can include copper, aluminum, nickel, gold, or other metals. The cooling metal layer has an enhanced surface facing away from the ceramic tile, where the enhanced surface includes either fins or pins. Electronic components can be connected to the substrate on a surface opposite the cooling metal layer.

Method for forming pattern and a semiconductor device

According to one embodiment, a pattern forming method comprises transferring a pattern formed in a surface of a template to a plurality of chip areas in a semiconductor substrate under different transfer conditions. Furthermore, the transferring the pattern formed in the surface of the template to the plurality of chip areas in the semiconductor substrate under the different transfer conditions comprises transferring the pattern formed in the surface of the template to the semiconductor substrate at least twice under each identical transfer condition. Moreover, the pattern forming method comprises dividing each of the plurality of chip areas into a plurality of areas, determining an optimum condition for each set of corresponding divided areas in the plurality of chip areas, and transferring the pattern onto the semiconductor substrate using the optimum transfer condition determined for each divided area.

Semiconductor device and method of fabricating the same

A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.

Methods of operating electronic devices, and methods of providing electronic devices

Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing.

Multi-Layer Circuit Assembly And Process For Preparing The Same

A process for fabricating a multi-layer circuit assembly is provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; (c) removing the dielectric coating in a predetermined pattern to expose sections of the substrate; (d) applying a layer of metal to all surfaces to form metallized vias through and/or to the electrically conductive core; (e) applying a resist to the metal layer to form a photosensitive layer thereon; (f) imaging resist in predetermined locations; (g) developing resist to uncover selected areas of the metal layer; and (h) etching uncovered areas of metal to form an electrical circuit pattern connected by the metallized vias.

Gas delivery system for reducing oxidation in wire bonding operations

A wire bonding machine is provided. The wire bonding machine includes a bonding tool and an electrode for forming a free air ball on an end of a wire extending through the bonding tool where the free air ball is formed at a free air ball formation area of the wire bonding machine. The wire bonding machine also includes a bond site area for holding a semiconductor device during a wire bonding operation. The wire bonding machine also includes a gas delivery mechanism configured to provide a cover gas to: (1) the bond site area whereby the cover gas is ejected through at least one aperture of the gas delivery mechanism to the bond site area, and (2) the free air ball formation area.

Image engine with integrated circuit structure for indicia reading terminal

Embodiments of the present invention comprise an image engine constructed as an IC structure that has one or more active regions for illuminating, imaging, and decoding a decodable indicia. In one embodiment of the image engine, the IC structure can comprise an imaging region, an aiming region, and an illumination region, all disposed on a single, contiguous substrate. The resultant constructed embodiment can fit within a form factor, wherein the form factor is less than about 500 mm 3 .

Metal semiconductor alloy structure for low contact resistance

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

Method for fabrication of a semiconductor device and structure

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Integrated circuit packaging system with die paddle and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.

High-voltage packaged device

Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Semiconductor device

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Self-aligned permanent on-chip interconnect structure formed by pitch splitting

A method of fabricating an interconnect structure is provided. The method includes forming a hybrid photo-patternable dielectric material atop a substrate. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to radiation. The hybrid photo-patternable dielectric material is then image-wise exposed to radiation such that a self-aligned pitch split pattern forms. A portion of the self-aligned split pattern is removed to provide a patterned hybrid photo-patternable dielectric material having at least one opening therein. The patterned hybrid photo-patternable dielectric material is then converted into a cured and patterned dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filed with at least an electrically conductive material. Also provided are a hybrid photo-patternable dielectric composition and an interconnect structure.

Systems and Methods for Heat Dissipation Using Thermal Conduits

The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

Battery heating circuits and methods with resonance components in series using voltage inversion based on predetermined conditions

Certain embodiments of the present invention provide a battery heating circuit, comprising a switch unit ( 1 ), a switching control module ( 100 ), a damping component R 1 , an energy storage circuit, and an energy superposition unit, the energy storage circuit is configured to connect with the battery to form a loop, and comprises a current storage component L 1 and a charge storage component C 1 ; the damping component R 1 , the switch unit ( 1 ), the current storage component L 1 , and the charge storage component C 1 are connected in series; the switching control module ( 100 ) is connected with the switch unit ( 1 ), and is configured to control ON/OFF of the switch unit ( 1 ), so as to control the energy flowing between the battery and the energy storage circuit; the energy superposition unit is connected with the energy storage circuit, and is configured to superpose the energy in the energy storage circuit with the energy in the battery when the switch unit ( 1 ) switches on and then switches off; the switching control module ( 100 ) is also configured to control the switch unit ( 1 ) to switch off after the first positive half cycle of current flow through the switch unit ( 1 ) after the switch unit ( 1 ) switches on, and the voltage applied to the switch unit ( 1 ) at the time the switch unit ( 1 ) switches off is lower than the voltage rating of the switch unit ( 1 ).

Gain Enhanced LTCC System-on-Package for UMRR Applications

An apparatus, system, and method for Gain Enhanced LTCC System-on-Package radar sensor. The sensor includes a substrate and an integrated circuit coupled to the substrate, where the integrated circuit is configured to transmit and receive radio frequency (RF) signals. An antenna may be coupled to the integrated circuit and a lens may be coupled to the antenna. The lens may be configured to enhance the gain of the sensor.

Diamond semiconductor element and process for producing the same

A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

Energy Conditioning Circuit Arrangement for Integrated Circuit

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK 1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK 2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK 1 +TK 2 ; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

Capillary and ultrasonic transducer for ultrasonic bonding

A capillary is attached to an ultrasonic transducer of a wire-bonding apparatus. The capillary includes a first part configured to be attached to the ultrasonic transducer, and a second part other than the first part and extending from the first part. The first part has a shape different from a shape of the second part so that the first part has a flexure rigidity larger than the second part.

Led package

A LED package includes a substrate, at least one LED chip, a transparent adhesive and a lens. The at least one LED chip is mounted on the substrate. The transparent adhesive is filled between the LED chip and the lens. A number of through holes is regularly defined in an optical non-effective portion of the lens. The through holes are configured for increasing the air convection between inside and outside of the lens.

Light emitting device

A light emitting device, which has: a light emitting element; a package that comprises a concavity for holding the light emitting element, and that has on its side wall where the concavity is integrally formed a light reflector for reflecting light from the light emitting element and a light transmitter for transmitting light from the light emitting element to the outside.

Semiconductor device with less power supply noise

A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

Semiconductor device with protective films and manufacturing method thereof

A semiconductor device includes a semiconductor substrate having a drain region, a source region and an impurity diffusion region; an oxide film formed on the impurity diffusion region; a first protective film including a SiN film as a principle component and being formed on the oxide film; and a second protective film containing carbon and being formed on the first protective film. A method of manufacturing the semiconductor device, includes doping an impurity into a semiconductor substrate, thereby forming a drain region, a source region and an impurity diffusion region; forming an oxide film on the impurity diffusion region; forming a first protective film including a SiN film as a principle component on the oxide film; and forming a second protective film containing carbon on the first protective film.

Semiconductor device

A semiconductor device includes a first semiconductor chip 1 , a second semiconductor chip 4 , a first lead frame 3 including a first die pad 9 on which the first semiconductor chip 1 is mounted, and a second lead frame 5 including a second die pad 11 on which the second semiconductor chip 4 is mounted. A sealing structure 6 covers the first semiconductor chip 1 and the second semiconductor chip 4 . A noise shield 7 is disposed between the first semiconductor chip 1 and the second semiconductor chip 4.

Structure for Multi-Row Leadframe and Semiconductor Package Thereof and Manufacture Method Thereof

The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Composite Electronic Circuit Assembly

A composite electronic circuit assembly comprises two MOS or CMOS circuit dice ( 100, 200 ) superimposed inside a package. Different modules of the circuit assembly are distributed between the two dice based on the digital, analog, or hybrid nature of said modules. Such a distribution makes it possible to group together the digital modules of the circuit assembly in one of the die and the analog or hybrid modules in the other die. The production cost, development time, and electrical energy consumption of the circuit assembly may thus be reduced.

Thermal expansion suppressing member and anti-thermally-expansive member

Provided are a thermal expansion suppressing member having negative thermal expansion properties and a metal-based anti-thermally-expansive member having small thermal expansion. More specifically, provided are a thermal expansion suppressing member, including at least an oxide represented by the following general formula (1), and an anti-thermally-expansive member, including a metal having a positive linear expansion coefficient at 20° C., and a solid body including at least an oxide represented by the following general formula (1), the metal and solid being joined to each other: (Bi 1-x M x )NiO 3 (1) where M represents at least one metal selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y, and In; and x represents a numerical value of 0.02≦x≦0.15.

Heat sink core member and its fabrication procedure

A heat sink core member made by: preparing a predetermined mass of aluminum block, extruding the aluminum block through an extruding machine into a tubular body having one close end wall and then punch-cutting the outside wall of the tubular body to form a plurality of densely distributed and equally spaced vertical retaining grooves. Radiation fins can easily be affixed to the vertical retaining grooves of the tubular body to form a heat sink.

Flexible circuit structure with stretchability and method of manufacturing the same

In one example embodiment, a flexible circuit structure with stretchability is provided that includes a flexible substrate, a plurality of flexible bumps formed on the flexible substrate, and a metal layer formed on the plurality of flexible bumps and the flexible substrate.

Semiconductor device and method for forming the same

The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

Nonvolatile semiconductor memory device and method for manufacturing same

In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Packaging Integrated Circuits

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Interconnects with improved tddb

A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

Power Managers for an Integrated Circuit

A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.

Authentication device, authentication method, and an information storage medium storing a program

There is provided an authentication device including an authentication information storage unit that stores authentication information acquired from an authentication pattern including a part or the entirety of a mottled pattern or a dot pattern formed over an electronic component as information for indentifying each of a plurality of electronic components, an authentication information acquiring unit that acquires a first authentication information acquired from the authentication pattern formed over a first electronic component that is an object to be authenticated, a search unit that searches whether or not the authentication information storage unit stores the first authentication information by using the first authentication information as a search key, and an output unit that outputs a search result of the search unit.

Metal-Ceramic Substrate

A metal/ceramic substrate made up of a multilayer, plate-shaped ceramic material and at least one metallization provided on a surface side of the ceramic material. The at least one metallization is bonded to the ceramic material by direct copper bonding or reactive brazing and the ceramic material is made of a base layer made of silicon nitride ceramic. The at least one metallization is formed from at least one intermediate layer of an oxidic ceramic applied to the at least one base layer.

Method of making interconnect structure

One or more embodiments relate to a method of forming a semiconductor device having a substrate, comprising: providing a Si-containing layer; forming a barrier layer over the Si-containing layer, the barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over the Si-containing layer, the nucleation_seed layer including the metallic element; and forming a metallic interconnect layer over the nucleation_seed layer, wherein the barrier layer and the nucleation_seed layer are formed without exposing the semiconductor device substrate to the ambient atmosphere.

Thermally conductive foam product

A compressible, thermally conductive foam interface pad is adapted for emplacement between opposed heat transfer surfaces in an electronic device. One heat transfer surface can be part of a heat-generating component of the device, while the other heat transfer surface can be part of a heat sink or a circuit board. An assembly including the foam interface pad and the opposed electronic components is also provided.

Semiconductor structures

Test structures are formed during semiconductor processing with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.

Light emitting device

The present disclosure provides a light emitting device, including a serially-connected LED array including a plurality of LED cells on a single substrate, including a first LED cell, a second LED cell, and a serially-connected LED sub-array including at least three LED cells intervening the first and second LED cell, wherein each of the first and second LED cell including a first side and a second side that the first side of the first LED cell and/or the second LED cell neighboring to the LED sub-array, and the second side of the first LED cell neighboring to the second side of the second LED cell; a trench between the second sides of the first and second LED cells; and a protecting structure formed near the trench to prevent the light-emitting device from being damaged near the trench by a surge voltage higher than a normal operating voltage of the light emitting device.

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Interconnect Structure for Semiconductor Devices

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.