Nanosheet-Feldeffekttransistor mit einem zweidimensionalen halbleitenden Material

Strukturen für einen Feldeffekttransistor und Verfahren zum Bilden von Strukturen für einen Feldeffekttransistor. In einem Schichtstapel ist eine Mehrzahl von Kanalschichten angeordnet und ein Source/Drain-Bereich ist mit der Vielzahl von Kanalschichten verbunden. Eine Gatestruktur umfasst eine Mehrzahl von Abschnitten, die jeweils die Mehrzahl von Kanalschichten umgeben. Die Mehrzahl von Kanalschichten umfasst ein zweidimensionales halbleitendes Material.

N-TYPE SEMICONDUCTOR DIAMOND PRODUCING METHOD AND SEMICONDUCTOR DIAMOND

Process for forming homoepitaxial tunnel barriers with hydrogenated graphene-on-graphene for room temperature electronic device applications

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same material—graphene.

Carbon nanotube transistor with carrier blocking using thin dielectric under contact

The subject embodiments relate to carbon nanotube (CNT) transistors with carrier blocking using thin dielectric under the drain or source and drain contacts. According to an embodiment, a transistor is provided that comprises a CNT channel layer, a metal source contact formed on the carbon nanotube channel layer, and a metal drain contact formed on the carbon nanotube channel layer. The transistor structure further comprises a drain dielectric layer formed adjacent to and between a lower surface of the metal drain contact and an upper surface of the carbon nanotube channel layer. In one or more implementations, the drain dielectric layer comprises a material that suppresses injection of a first type of carrier into the CNT channel layer and facilitates the injection of a second type of carrier into the CNT channel layer.

Heteroatom-containing diamondoid transistors

A semiconductor device

A THERMAL OR INFRARED SENSING APPARATUS

An apparatus comprising: pyroelectric material;an electric field sensor;a first conductive electrode comprising a first area adjacent the pyroelectric material;a second conductive electrode comprising a second area adjacent the electric field sensor;and a conductive interconnection between the first conductive electrode and the second conductive electrode,wherein the first area of the first conductive electrode is larger than the second area of the second conductive electrode.

PROCEEDED Of MAKING OF DIAMOND OF the TYPE NR HAS HIGH ELECTRIC CONDUCTIVITY

질화규소에 비해 p-도핑된 폴리실리콘을 선택적으로 에칭하기 위한 조성물 및 방법

... 상부에 p-도핑된 폴리실리콘 (예를 들어, 붕소-도핑된 폴리실리콘) 및 질화규소를 갖는 마이크로전자 디바이스로부터 질화규소에 비해 p-도핑된 폴리실리콘 (예를 들어, 붕소-도핑된 폴리실리콘)을 선택적으로 제거하기 위한 제거 조성물 및 방법. 기판은 바람직하게는 고-k/금속 게이트 통합 체계를 포함한다.

HEAVILY DOPED REGION IN DOUBLE-DIFFUSED SOURCE MOSFET (LDMOS) TRANSISTOR AND A METHOD OF FABRICATING THE SAME

A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.

CARBON NANOTUBE TRANSISTOR WITH CARRIER BLOCKING USING THIN DIELECTRIC UNDER CONTACT

The subject embodiments relate to carbon nanotube (CNT) transistors with carrier blocking using thin dielectric under the drain or source and drain contacts. According to an embodiment, a transistor is provided that comprises a CNT channel layer, a metal source contact formed on the carbon nanotube channel layer, and a metal drain contact formed on the carbon nanotube channel layer. The transistor structure further comprises a drain dielectric layer formed adjacent to and between a lower surface of the metal drain contact and an upper surface of the carbon nanotube channel layer. In one or more implementations, the drain dielectric layer comprises a material that suppresses injection of a first type of carrier into the CNT channel layer and facilitates the injection of a second type of carrier into the CNT channel layer. 1. A transistor , comprising:a carbon nanotube channel layer;a metal source contact formed on the carbon nanotube channel layer;a metal drain contact formed on the carbon nanotube channel layer; anda drain dielectric layer formed adjacent to and between a lower surface of the metal drain contact and an upper surface of the carbon nanotube channel layer, wherein the drain dielectric layer contacts the upper surface of the carbon nanotube layer and further contacts an entirety of the lower surface of the metal drain contact.2. (canceled)3. The transistor of claim 1 , wherein the drain dielectric layer comprises a material that suppresses injection of a first type of carrier into the carbon nanotube channel layer and facilitates the injection of a second type of carrier into the carbon nanotube channel layer.4. The transistor of claim 1 , wherein the drain dielectric layer comprises a material that allows passage of a first type of carrier through the drain dielectric layer at a higher rate relative to a second type of carrier.5. The transistor of claim 1 , wherein the drain dielectric layer comprises a material with a conduction band offset and ...

N-TYPE SEMICONDUCTOR DIAMOND PRODUCING METHOD AND SEMICONDUCTOR DIAMOND

An n-type semiconductor diamond producing method, an n-type semiconductor diamond, pn-junction semiconductor diamond, a pnp-junction semiconductor diamond, an npn-junction semiconductor diamond, and a pin-junction are provided. A diamond {100} single-crystal substrate (10) is processed to form a diamond {111} surface. A diamond is epitaxially grown while the diamond {111} surface is being doped with an n-type dopant to form an n-type diamond epitaxial layer (20). Combining a thus produced n-type semiconductor diamond, a p-type semiconductor diamond, and a non-doped diamond, and using a p-type semiconductor diamond {100} single-crystal substrate, a pn-junction semiconductor diamond, a pnp-junction semiconductor diamond, an npn-junction semiconductor diamond, and a pin-junction semiconductor diamond are produced.

Composition and Process for Selectively Etching P-Doped Polysilicon Relative to Silicon Nitride

A removal composition and process for selectively removing p-doped polysilicon (e.g., boron-doped polysilicon) relative to silicon nitride from a microelectronic device having said material thereon. The substrate preferably comprises a high-k/metal gate integration scheme.

Apparatus and method for controlling doping

An apparatus and method, the apparatus comprising: at least one charged substrate (3); a channel of two dimensional material (5); and at least one floating electrode (7A-C) wherein the floating electrode comprises a first area (10A-C) adjacent the at least one charged substrate, a second area (11A-C) adjacent the channel of two dimensional material and a conductive interconnection (9A-C) between the first area and the second area wherein the first area is larger than the second area and wherein the at least one floating electrode is arranged to control the level of doping within the channel of two dimensional material.

Ein Verfahren zum Bilden eines Halbleiterbauelements

Ein Verfahren zum Bilden eines Halbleiterbauelements umfasst das Bilden einer amorphen oder polykristallinen Halbleiterschicht benachbart zu zumindest einer Halbleiterdotierungsregion mit einem ersten Leitfähigkeitstyp, die in einem Halbleitersubstrat angeordnet ist. Das Verfahren umfasst ferner das Einbringen von Dotierstoffen in die amorphe oder polykristalline Halbleiterschicht während oder nach dem Bildern der amorphen oder polykristallinen Halbleiterschicht. Das Verfahren umfasst ferner das Ausheilen der amorphen oder polykristallinen Halbleiterschicht, um zumindest einen Teil der amorphen oder polykristallinen Halbleiterschicht in eine im Wesentlichen monokristalline Halbleiterschicht zu transformieren, und um zumindest eine Dotierungsregion mit dem zweiten Leitfähigkeitstyp in der monokristallinen Halbleiterschicht derart zu bilden, dass ein p-n-Übergang zwischen der zumindest einen Halbleiterdotierungsregion mit dem ersten Leitfähigkeitstyp und der zumindest einen Dotierungsregion ...

METHOD FOR N-DOPING GRAPHENE

The present invention provides a method for n-doping graphene, an n-doped graphene prepared thereby, and an element including the n-dope graphene, the method comprising: a step of growing the graphene on a substrate by supplying a reaction gas containing a carbon source and heat on the substrate and reacting same; and n-doping the graphene by means of a doping solution or a vapor containing an n-type dopant.

Thermal diffusion doping of diamond

Boron-doped diamond and methods for making it are provided. The doped diamond is made using an ultra-thin film of heavily boron-doped silicon as a dopant carrying material in a low temperature thermal diffusion doping process.

Roll-to-roll doping method of graphene film, and doped graphene film

The present disclosure relates to roll-to-roll doping method of graphene film, and doped graphene film.

A SENSING APPARATUS

An apparatus comprising: pyroelectric material;an electric field sensor;a first conductive electrode comprising a first area adjacent the pyroelectric material;a second conductive electrode comprising a second area adjacent the electric field sensor;and a conductive interconnection between the first conductive electrode and the second conductive electrode,wherein the first area of the first conductive electrode is larger than the second area of the second conductive electrode.

HETEROATOM-CONTAINING DIAMONDOID TRANSISTORS

Novel heterodiamondoids are disclosed. These heterodiamondoids are diamondoids that include heteroatoms in the diamond lattice structure. The heteroatoms may be either electron donating, such that an n-type heterodiamondoid is created, or electron withdrawing, such that a p-type heterodiamondoid is made. Bulk materials may be fabricated from these heterodiamondoids, and the techniques involved include chemical vapor deposition, polymerization, and crystal aggregation. Junctions may be made from the p-type and n-type heterodiamondoid based materials, and microelectronic devices may be made that utilize these junctions. The devices include diodes, bipolar junction transistors, and field effect transistors.

N-TYPE SEMICONDUCTOR DIAMOND PRODUCING METHOD AND SEMICONDUCTOR DIAMOND

An n-type semiconductor diamond producing method, an n-type semiconductor diamond, pn-junction semiconductor diamond, a pnp-junction semiconductor diamond, an npn-junction semiconductor diamond, and a pin-junction are provided. A diamond {100} single-crystal substrate (10) is processed to form a diamond {111} surface. A diamond is epitaxially grown while the diamond {111} surface is being doped with an n-type dopant to form an n-type diamond epitaxial layer (20). Combining a thus produced n-type semiconductor diamond, a p-type semiconductor diamond, and a non-doped diamond, and using a p-type semiconductor diamond {100} single-crystal substrate, a pn-junction semiconductor diamond, a pnp-junction semiconductor diamond, an npn-junction semiconductor diamond, and a pin-junction semiconductor diamond are produced.

Heavily doped region in double-diffused source MOSFET (LDMOS) transistor and a method of fabricating the same

A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.

Production of n type diamond, doped with boron and hydrogen by diffusion under vacuum, for use as semiconductor substitute to silicon

Procédé de fabrication d'un diamant de type n comprenant une étape de dopage n, dans laquelle on fait diffuser sous vide une espèce donneuse dans un diamant initialement dopé par un accepteur (12), pour y former des groupes donneurs contenant l'espèce donneuse, à une température inférieure ou égale à la température de dissociation de complexes formés entre l'accepteur et l'espèce donneuse.

Compositions and methods for selectively etching p- doped polysilicon relative to silicon nitride

Boron-doped nanocrystalline diamond

A conductive boron doped nanocrystalline diamond is described. The boron doped diamond has a conductivity which uses the boron in the crystals as a charge carrier. The diamond is particularly useful for electrochemical electrodes in oxidation-reduction reactions and decontamination of aqueous solutions.

ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE

Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials.

METHOD FOR N-DOPING GRAPHENE

The present disclosure provides an n-doping method of graphene, including supplying a reaction gas containing a carbon source and heat to a substrate and reacting to grow graphene on the substrate; and n-doping the graphene by a doping solution containing an n-type dopant or a vapor containing an n-type dopant, an n-doped graphene produced by the method, and a device including the n-doped graphene. 1. An n-doping method of graphene , comprising:supplying a reaction gas containing a carbon source and heat to a substrate and reacting to grow graphene on the substrate; andn-doping the graphene by a doping solution containing an n-type dopant or a vapor containing an n-type dopant.2. The n-doping method of graphene of claim 1 ,wherein the n-doping of the graphene includes dropping the doping solution containing the n-type dopant on the graphene to form a liquid doping layer.3. The n-doping method of graphene of claim 1 ,wherein the n-doping of the graphene includes installing the graphene grown on the substrate in a reaction chamber and supplying the vapor containing the n-type dopant in the reaction chamber.4. The n-doping method of graphene of claim 1 ,wherein the n-type dopant includes an amine compound or a reducing agent.5. The n-doping method of graphene of claim 4 ,{'sub': 3', '2', '2', '5', '5', '4', '5', '3, 'wherein the amine compound includes one selected from the group consisting of ammonia (NH), hydrazine (NHNH), pyridine (CHN), pyrrole (CHN), acetonitrile (CHCN), triethanolamine, aniline, and combinations thereof.'}6. The n-doping method of graphene of claim 4 ,{'sub': 4', '4, 'wherein the reducing agent includes one selected from the group consisting of NaBH, LiAl, hydroquinones, and combinations thereof.'}7. The n-doping method of graphene of claim 1 ,wherein the substrate has one or more properties among transparency, flexibility, and extendibility.8. The n-doping method of graphene of claim 1 ,wherein the substrate further includes a catalytic layer.9. ...

SEMICONDUCTOR DEVICE

Although in the semiconductor device using a hetero junction including an electron transport layer of GaN and an electron supply layer of AlGaN, etc. normally off can be made by forming a p-type layer between the electron supply layer and a gate electrode, on-resistance is high because the surface of the electron supply layer becomes rough when forming the p-type layer in a local area. To solve this problem, an insulation layer covering the surface of the electron supply layer exposed between the source electrode and the p-type layer and the surface of the electron supply layer exposed between the drain electrode and the p-type layer can be charged positive. Thus, two-dimensional electron gas concentration applied to the hetero junction rises so that the on-resistance can be lowered. COPYRIGHT KIPO 2016 ...

Cmos well structure and method of forming the same

HETEROATOM-CONTAINING DIAMONDOID TRANSISTORS

Novel heterodiamondoids are disclosed. These heterodiamondoids are diamondoids that include heteroatoms in the diamond lattice structure. The heteroatoms may be either electron donating, such that an n-type heterodiamondoid is created, or electron withdrawing, such that a p-type heterodiamondoid is made. Bulk materials may be fabricated from these heterodiamondoids, and the techniques involved include chemical vapor deposition, polymerization, and crystal aggregation. Junctions may be made from the p-type and n-type heterodiamondoid based materials, and microelectronic devices may be made that utilize these junctions. The devices include diodes, bipolar junction transistors, and field effect transistors.

Organic light emitting display having compensation for transistor threshold variation

An organic light emitting display including a demux is disclosed. The display include a plurality of RGB switching transistors which apply a data voltage through RGB data lines as the RGB switching transistors are coupled to the respective RGB data lines, and a plurality of RGB pixel circuits coupled to the RGB switching transistors of the demux. In addition, the RGB data voltage of the demux can be applied during a period which a turn-on emission control signal is applied to the RGB pixel circuits.

Structure of MTCMOS cell

An architecture of the layout of the MTCMOS standard cell designed for low power consumption is supplemented so that the pick-up cells are included in the power line of the MTCMOS cell. Therefore, when the logic circuit is constructed using the library layout of the MTCMOS cell in which the related pick-up cells are not included, pick-up cells consisting of only the ends of the pick-up cells are not needed every 50 m during the placement of the MTCMOS standard cell. The flexibility of the cell placement may thereby be improved. In addition, since additional space for the pick-up cells is not required, the size of the MTCMOS may be reduced, saving space on the semiconductor substrate.

HALBLEITERBAUELEMENT UND VERFAHREN ZUM HERSTELLEN EINES HALBLEITERBAUELEMENTS

Ein aktiver Zellbereich, ein Randabschlussbereich, der den aktiven Zellbereich umgibt, und ein Zwischenbereich, der an einer Zwischenposition zwischen diesen Bereichen angeordnet ist, werden bereitgestellt, wobei der aktive Zellbereich eine MOS-Struktur vom Trench-Gate-Typ an einer Oberseite aufweist, und eine Vertikalstruktur an einer Unterseite eine p-Kollektorschicht, eine n-Pufferschicht an der p-Kollektorschicht und eine n-Driftschicht an der n-Pufferschicht aufweist, die n-Pufferschicht einen ersten Pufferabschnitt, der auf der p-Kollektorseite vorhanden ist, und einen zweiten Pufferabschnitt, der auf der n-Driftschichtseite vorhanden ist, aufweist, die Spitzenverunreinigungskonzentration des ersten Pufferabschnitts höher ist als die Spitzenverunreinigungskonzentration des zweiten Pufferabschnitts, und der Verunreinigungskonzentrationsgradient auf der n-Driftschichtseite des zweiten Pufferabschnitts schwächer ist als der Verunreinigungskonzentrationsgradient auf der n-Driftschichtseite ...

Method of providing an air- and/or moisture-barrier coating on a two dimensional material

A method of providing an air or moisture barrier coating 215 on a two-dimensional material 205 comprises providing a substrate 200 having a two-dimensional material, preferably a graphene layer structure, thereon, providing a composition comprising an inorganic oxide, fluoride or sulphide precursor and a doping agent, coating the composition 210 onto at least a portion of the material, and curing or annealing the coated material at a temperature of no greater than 1200°C, wherein the doping agent dopes the two-dimensional material 220. The doping agent is preferably an organic doping agent, such as a carboxylic acid or a conjugated hydrocarbon. The composition preferably comprises an inorganic oxide precursor, wherein the oxide is silicon dioxide or titanium oxide. The substrate may be an insulator or a semiconductor material. The method may further comprise laser etching the two-dimensional material prior to the coating step, wherein the etching forms a Hall sensor.

AN APPARATUS AND METHOD FOR CONTROLLING DOPING

An apparatus and method, the apparatus comprising: at least one charged substrate (3); a channel of two dimensional material (5); and at least one floating electrode (7A-C) wherein the floating electrode comprises a first area (10A-C) adjacent the at least one charged substrate, a second area (11A-C) adjacent the channel of two dimensional material and a conductive interconnection (9A-C) between the first area and the second area wherein the first area is larger than the second area and wherein the at least one floating electrode is arranged to control the level of doping within the channel of two dimensional material.

Low-temperature oxide method for manufacturing backside field stop layer of insulated gate bipolar transistor (IGBT)

A low-temperature oxide method is used for manufacturing backside field stop layer of insulated gate bipolar transistor (IGBT) and first fabricates front elements and front metal layer on a first face of a first conductive type substrate. A multiple-recesses structure is formed on a back side of the first conductive type substrate. Each of the recess in the multiple-recesses structure has first conductive type implanted patterns on exterior sides thereof and the multiple-recesses structure has a first conductive type implanted layer on bottom thereof. A plurality of first conductive type polysilicon layers are deposited into the multiple-recesses structure and respectively corresponding to the first conductive type implanted patterns. A second first conductive type impurity layer is formed on the bottom of the first conductive type substrate and laser annealing is conducted to form backside field stop layer for IGBT.

ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE

Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.

HETEROATOM-CONTAINING DIAMONDOID TRANSISTORS

Method of producing an n-type diamond with high electrical conductivity

METHOD OF PRODUCING AN N-TYPE DIAMOND WITH HIGH ELECTRICAL CONDUCTIVITY

SILICON CARBIDE EPI WAFER AND SEMICONDUCTOR DEVICE COMPRISING SAME

A silicon carbide epi wafer according to an embodiment includes: a base substrate; a first epi layer disposed on the base substrate and having a groove formed therein; and a second epi layer disposed in the groove, wherein the first epi layer has an N-type characteristic and the second epi layer has a P-type characteristic. Accordingly, a semiconductor device can increase a breakdown voltage and reduce a leakage current. COPYRIGHT KIPO 2017 ...

HETEROATOM-CONTAINING DIAMONDOID TRANSISTORS

Novel heterodiamondoids are disclosed. These heterodiamondoids are diamondoids that include heteroatoms in the diamond lattice structure. The heteroatoms may be either electron donating, such that an n-type heterodiamondoid is created, or electron withdrawing, such that a p-type heterodiamondoid is made. Bulk materials may be fabricated from these heterodiamondoids, and the techniques involved include chemical vapor deposition, polymerization, and crystal aggregation. Junctions may be made from the p-type and n-type heterodiamondoid based materials, and microelectronic devices may be made that utilize these junctions. The devices include diodes, bipolar junction transistors, and field effect transistors. © KIPO & WIPO 2007 ...

INSULATED GATE BIPOLAR TRANSISTOR

Disclosed is an insulated gate bipolar transistor having improved planar gate structure. The insulated gate bipolar transistor includes: a P+ collector layer formed with a depth of 0.5 um; an N_drift layer formed on the upper surface of the P+ collector layer with a depth of 100 um; a P_base layer formed on the upper surface of the N_drift layer with a depth of 3.5 um; a P+ layer formed on the upper surface of the P_base layer with a depth of 0.8 um; an N+ layer with a width of 1 um on the upper side of the P_base layer; and a gate layer with a width of 4 um on the upper side of the N_drift layer. COPYRIGHT KIPO 2017 ...

Semiconductor device and method for fabricating the same

HETEROATOM-CONTAINING DIAMONDOID TRANSISTORS

Novel heterodiamondoids are disclosed. These heterodiamondoids are diamondoids that include heteroatoms in the diamond lattice structure. The heteroatoms may be either electron donating, such that an n-type heterodiamondoid is created, or electron withdrawing, such that a p-type heterodiamondoid is made. Bulk materials may be fabricated from these heterodiamondoids, and the techniques involved include chemical vapor deposition, polymerization, and crystal aggregation. Junctions may be made from the p-type and n-type heterodiamondoid based materials, and microelectronic devices may be made that utilize these junctions. The devices include diodes, bipolar junction transistors, and field effect transistors.

Trench MOSFET device with polycrystalline silicon source contact structure

A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and ( ...

SEMICONDUCTOR RECTIFIER AND MANUFACTURING METHOD THEREOF

A semiconductor rectifying device and a method of manufacturing the same. The semiconductor rectifying device includes: a substrate of a first conductivity type ( 100 ), an epitaxial layer of a first conductivity type ( 200 ) formed on the substrate of the first conductivity type ( 100 ), wherein the epitaxial layer of the first conductivity type ( 200 ) defines a plurality of trenches ( 310 ) thereon; a filling structure ( 300 ) comprising an insulating material formed on the inner surface of the trench ( 310 ) and a conductive material filled in the trench ( 310 ); a doped region of a second conductivity type ( 400 ) formed in the surface of the epitaxial layer of the first conductivity type ( 200 ) located between the filling structures ( 300 ); an upper electrode ( 600 ) formed on a surface of the epitaxial layer of the first conductivity type ( 200 ); a guard ring ( 700 ) formed in the surface layer of the epitaxial layer of the first conductivity type ( 200 ); and a guard layer ( 800 ).

Semiconductor device and method of manufacturing the same

A semiconductor device of an embodiment includes a p-type first diamond semiconductor layer, a p-type second diamond semiconductor layer disposed on the first diamond semiconductor layer, a plurality of n-type third diamond semiconductor layers disposed on the second diamond semiconductor layer, and a first electrode disposed on the second diamond semiconductor and the third diamond semiconductor layers. The p-type second diamond semiconductor layer has a p-type impurity concentration lower than a p-type impurity concentration of the first diamond semiconductor layer and has oxygen-terminated surfaces. Each of the third diamond semiconductor layers has an oxygen-terminated surface. The first electrode forms first junctions between the first electrode and the second diamond semiconductor. The first electrode forms second junctions between the first electrode and the third diamond semiconductor layers. The first junctions and the second junctions are Schottky junctions.

CMOS well structure and method of forming the same

A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

TRENCH MOSFET DEVICE WITH POLYCRYSTALLINE SILICON SOURCE CONTACT STRUCTURE

ROLL-TO-ROLL DOPING METHOD OF GRAPHENE FILM AND DOPED GRAPHENE FILM

본원은 대면적 그래핀 필름의 롤투롤 도핑 방법 및 상기 방법에 의한 도핑된 그래핀 필름에 관한 것으로서, 상기 도핑 방법은 그래핀 필름을 롤투롤 공정을 이용하여 도펀트를 포함하는 도핑 용액 또는 도펀트 증기 내로 통과하도록 함으로써 상기 그래핀 필름을 도핑하는 것을 포함하는, 그래핀 필름의 롤투롤 도핑 방법을 제공한다. The present application relates to a roll-to-roll doping method of a large-area graphene film and a doped graphene film according to the method, wherein the doping method is used to convert the graphene film into a doping solution or a dopant vapor containing a dopant using a roll-to-roll process. It provides a roll-to-roll doping method of the graphene film, including doping the graphene film by passing through.

DIAMOND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF

L'invention concerne un dispositif à semi-conducteur en diamant présentant une jonction p-n permettant une rectification à haute température. Une couche de cristal (4) de diamant à semi-conducteur de type n dopé au soufre en tant que donneur et tirée sur un cristal (2) en diamant à semi-conducteur de type b constitué de diamant synthétique sous haute pression dopé au bore ou de diamant IIb naturel, par exemple, par un procédé de dépôt chimique en phase vapeur au plasma pour former une jonction p-n (6). La jonction p-n est capable d'une rectification à une température pouvant aller jusqu'à 500 °C.

FIELD EFFECT TRANSISTOR USING GRAPHENE, PHOSPHORUS-DOPED GRAPHENE, AND METHODS OF PRODUCING THE SAME

A field effect transistor using a channel layer including a phosphorus-doped graphene and a method of fabricating the same are provided. Further, a phosphorus-doped graphene and a method of producing the same are provided. The field effect transistor includes: a source electrode and a drain electrode formed on a substrate; and a channel layer comprising a phosphorus-doped graphene, the channel layer electrically connected to the source electrode and the drain electrode.

Electronic field effect devices and methods for their manufacture

Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials.

Method of preparing nitrogen-doped graphene

An exemplary method of preparing nitrogen-doped graphene whereby it is possible to synthesize graphene having an improved surface coverage and a uniform single layer, and to prepare high quality graphene in a large area. In addition, an aromatic compound containing nitrogen can be used as a carbon source and nitrogen-doped graphene can be thus synthesized as nitrogen doped in the synthesis process. It is possible to control the electrical properties of graphene depending on the nitrogen doping.

CMOS WELL STRUCTURE AND METHOD OF FORMING THE SAME

A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

Layered structures

도핑을 제어하기 위한 장치 및 방법

... 방법 및 장치가 개시되고, 상기 장치는: 적어도 하나의 충전된 기판(3); 2차원 재료(5)의 채널; 및 적어도 하나의 플로팅 전극(floating electrode)(7A 내지 C)을 포함하고, 플로팅 전극은 적어도 하나의 충전된 기판에 인접한 제 1 영역(10A 내지 C), 2차원 재료의 채널에 인접한 제 2 영역(11A 내지 C) 및 제 1 영역과 제 2 영역 사이의 전도성 상호접속부(9A 내지 C)를 포함하고, 제 1 영역은 제 2 영역보다 크며 적어도 하나의 플로팅 전극은 2차원 재료의 채널 내의 도핑 레벨을 제어하도록 배열된다.

N-DOPING METHOD OF GRAPHENE

반도체 장치

... (과제) GaN 의 전자 주행층과 AlGaN 등의 전자 공급층의 헤테로 접합을 이용하는 반도체 장치에서는, 전자 공급층과 게이트 전극 사이에 p 형층을 형성함으로써 노멀리 오프로 할 수 있지만, 국소적 범위에 p 형층을 형성할 때 전자 공급층의 표면이 거칠어져 온 저항이 높다. (해결 수단) 소스 전극과 p 형층 사이에 노출되는 전자 공급층의 표면과, 드레인 전극과 p 형층 사이에 노출되는 전자 공급층의 표면을 피복하는 절연층을 정(正)으로 대전시킨다. 헤테로 접합면에 유기되는 2 차원 전자 가스 농도가 상승하여, 온 저항이 저하된다.

METHOD FOR N-DOPING GRAPHENE CAPABLE OF USING N-TYPE DOPANT CONTAINING DOPING LIQUID OR N-TYPE DOPANT CONTAINING VAPOR WITHOUT A SEPARATE DOPING UNIT

PURPOSE: A method for n-doping graphene is provided to easily dope large sized graphene by using an amine compound or a material with reducibility as n-type dopant. CONSTITUTION: A method for n-doping graphene includes the following: graphene(20) is grown on a substrate(10) by reacting reaction gas containing carbon sources and heat on the substrate; the graphene is n-doped based on n-type dopant containing doping liquid(30) or n-type dopant containing vapor; and the n-type doping liquid is dropped on the graphene to form a liquid doped layer on the graphene. COPYRIGHT KIPO 2013 [Reference numerals] (AA) Doping ...

METHOD FOR N-DOPING GRAPHENE

The present invention provides a method for n-doping graphene, an n-doped graphene prepared thereby, and an element including the n-dope graphene, the method comprising: a step of growing the graphene on a substrate by supplying a reaction gas containing a carbon source and heat on the substrate and reacting same; and n-doping the graphene by means of a doping solution or a vapor containing an n-type dopant.

Chemical sensors based on plasmon resonance in graphene

Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided.

Composition and process for selectively etching p-doped polysilicon relative to silicon nitride

A removal composition and process for selectively removing p-doped polysilicon (e.g., boron-doped polysilicon) relative to silicon nitride from a microelectronic device having said material thereon. The substrate preferably comprises a high-k/metal gate integration scheme.

Method of fabricating n-type semiconductor diamond, and semiconductor diamond

An n-type diamond epitaxial layer 20 is formed by processing a single-crystalline {100} diamond substrate 10 so as to form a {111} plane, and subsequently by causing diamond to epitaxially grow while n-doping the diamond {111} plane. Further, a combination of the n-type semiconductor diamond, p-type semiconductor diamond, and non-doped diamond, obtained in the above-described way, as well as the use of p-type single-crystalline {100} diamond substrate allow for a pn junction type, a pnp junction type, an npn junction type and a pin junction type semiconductor diamond to be obtained.

Method for thermally processing a substrate and associated system

A method for thermally processing a substrate having a surface region and a buried region with a pulsed light beam, the substrate presenting an initial temperature-depth profile and the surface region presenting an initial surface temperature, including steps of: illuminating the surface region with a preliminary pulse so that it generates an amount of heat and reaches a predetermined preliminary surface temperature; and illuminating the surface region with a subsequent pulse after a time interval so that it reaches a predetermined subsequent surface temperature. The time interval is determined such that the surface region reaches a predetermined intermediate surface temperature greater than the initial surface temperature, such that during the time interval, the amount of heat is diffused within the substrate down to a predetermined depth so that the substrate presents a predetermined intermediate temperature-depth profile.

ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE

HIGH UNIFORMITY BORON DOPED DIAMOND MATERIAL

Layered structures

반도체 디바이스를 형성하는 방법

... 반도체 디바이스를 형성하는 방법은 반도체 기판 내에 위치된 제1 도전 유형을 가지는 적어도 하나의 반도체 도핑 영역에 인접하여 비정질 또는 다결정 반도체 층을 형성하는 단계를 포함한다. 방법은 비정질 또는 다결정 반도체 층을 형성하는 동안 또는 후에 비정질 또는 다결정 반도체 층 내에 도펀트를 혼입하는 단계를 더 포함한다. 방법은 비정질 또는 다결정 반도체 층을 어닐링하여, 비정질 또는 다결정 반도체 층의 적어도 일부를 실질적 단결정 반도체 층으로 변환하고 단결정 반도체 층 내에 제2 도전 유형을 가지는 적어도 하나의 도핑 영역을 형성하여, 제1 도전 유형을 가지는 적어도 하나의 반도체 도핑 영역 및 제2 도전 유형을 가지는 적어도 하나의 도핑 영역 간에 p-n 접합이 형성되게 하는 단계를 더 포함한다.

METHOD FOR FORMING SEMICONDUCTOR DEVICE

A method of forming a semiconductor device includes a step of forming an amorphous or polycrystalline semiconductor layer adjacent to at least one semiconductor doping region having a first conductivity type located in a semiconductor substrate. The method further comprises a step of adding a dopant to the amorphous or polycrystalline semiconductor layer during or after forming the amorphous or polycrystalline semiconductor layer. The method includes a step of annealing the amorphous or polycrystalline semiconductor layer to convert at least a portion of the amorphous or polycrystalline semiconductor layer into a substantially single crystalline semiconductor layer and form at least one doping region having a second conductivity type in the single crystal semiconductor layer, and forming p-n junction between at least one semiconductor doping region having a first conductivity type and at least one doping region having a second conductivity type. So, the stability to avalanche conditions ...

LAYERED STRUCTURES

A process of making a product which comprises at least two layers in contact with each other, each layer being of a wide-gap material and each layer differing from each other in at least one property, includes the steps of: (i) providing a substrate of a wide-band gap material having a surface and a region adjacent the surface having a particular characteristic, (ii) ion implanting the substrate through the surface to form a damaged layer below that surface, (iii) growing a layer of a wide-band gap material by chemical vapour deposition on at least a portion of the surface of the substrate through which ion implantation occurred, the material of the grown layer having a characteristic different to that of the region of the substrate adjacent the surface through which ion implantation occurred, and (iv) severing the substrate through the damaged layer.The wide-gap material is preferably diamond.

Layered structures

A process of making a product which comprises at least two layers in contact with each other, each layer being of a wide-gap material and each layer differing from each other in at least one property, includes the steps of: (i) providing a substrate of a wide-band gap material having a surface and a region adjacent the surface having a particular characteristic, (ii) ion implanting the substrate through the surface to form a damaged layer below that surface, (iii) growing a layer of a wide-band gap material by chemical vapour deposition on at least a portion of the surface of the substrate through which ion implantation occurred, the material of the grown layer having a characteristic different to that of the region of the substrate adjacent the surface through which ion implantation occurred, and (iv) severing the substrate through the damaged layer. The wide-gap material is preferably diamond.

PHOTO RESIST (PR) PROFILE CONTROL

One or more techniques or systems for controlling a profile for photo resist (PR) are provided herein. In some embodiments, a first shield layer is formed on a first PR layer and a second PR layer is formed on the first shield layer. A first window is formed within the second PR layer during a first exposure with a mask. A second window is formed within the first shield layer based on the first window. A third window is formed within the first PR layer during a second exposure without a mask. Because, the third window is formed while the first shield layer and the second PR layer are on the first PR layer, a profile associated with the first PR layer is controlled. Contamination during ion bombardment is mitigated due to the controlled profile.

POLARITY SWITCHING MEMBER OF DOT INVERSION SYSTEM

A polarity switching member of a dot inversion system is revealed. A first transistor and a second transistor are disposed in a P-well while a N-well is arranged in the P-well, located between the first transistor and the second transistor. The N-well includes a third transistor and a fourth transistor. One end of the third transistor is coupled to one end of the first transistor to generate a first input end and one end of the fourth transistor is coupled to one end of the second transistor to generate a second input end. The other end of the first transistor, the other end of the second transistor, the other end of the third transistor, and the other end of the fourth transistor are coupled to generate an output end. Thereby, by switching of voltage polarity of the P-well and the N-well, a larger range of output voltage difference is achieved.

LIGHT SOURCE AND METHOD FOR PRODUCING A LIGHT SOURCE

The invention relates to a light source comprising at least one p-n-junction which is formed by the arrangement of two suitable semi-conductor materials for the induced emission of light. Said light source is embodied and improved in such a manner that at least one of the semi-conductor materials is in the form of particles, such that a particularly large amount of light can be produced. The invention further relates to a method for producing said type of light source.

Semiconductor device

A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer.

산화물 반도체 기판 및 쇼트키 배리어 다이오드

... n 형 또는 p 형 실리콘 (Si) 기판과, 산화물 반도체층과, 쇼트키 전극층을 갖는 쇼트키 배리어 다이오드 소자로서, 상기 산화물 반도체층이 갈륨 (Ga) 을 주성분으로 하는 다결정 산화물 및 비정질 산화물 중 어느 일방 또는 양방을 함유하는 쇼트키 배리어 다이오드 소자.

A method of manufacturing a semiconductor device

Light-emitting organic diode comprising not more than two layers of different organic materials

The diode comprises: a first layer based on a first organic material, which is n-doped in a zone of this layer that is in contact with a cathode, a second layer based on a second organic material, which is p-doped in a zone of this layer that is in contact with an anode, and an electroluminescent zone which is incorporated in one of the layers and is in contact with the other layer, and which is neither n-doped nor p-doped. A high-yield diode is thus obtained in a particularly economical way.

HIGH UNIFORMITY BORON DOPED DIAMOND MATERIAL

The present invention relates to diamond material comprising a boron doped single crystal diamond substrate layer having a first surface and a boron doped single crystal diamond conductive layer on said first surface, wherein the distribution of boron in the conductive layer is more uniform than the distribution of boron in the substrate layer.

SYSTEMS AND METHODS FOR UNIVERSAL DEGENERATE P-TYPE DOPING WITH MONOLAYER TUNGSTEN OXYSELENIDE (TOS)

Disclosed are compositions and methods of semiconductors including tungsten oxyselenide (TOS) as a p-type dopant. The TOS is formed by introducing a single layer of tungsten diselenide (WSe2) to a semiconductor and subject the tungsten diselenide to a room-temperature UV plus ozone process. This process forms a TOS monolayer, which can be used as a universal p-type dopant for a variety of different semiconductors. Suitable semiconductor materials include, for example, graphene, carbon nanotubes, tungsten diselenide, and dinaphthothienothiophene (DNTT).

PLASMA ETCHING OF DIAMOND SURFACES

The present invention relates to a method of producing a diamond surface including the steps of providing an original diamond surface, subjecting the original diamond surface to plasma etching to remove at least 2 nm of material from the original surface and produce a plasma etched surface, the roughness Rq of the plasma etched surface at the location of the etched surface where the greatest depth of material has been removed satisfying at least one of the following conditions: Rq of the plasma etched surface is less than 1.5 times the roughness of Rq of the original surface, or Rq of the plasma etched surface is less than 1 nm.

Verfahren zum Dotieren einer Graphen-Schicht

Die Erfindung betrifft ein Verfahren zum Dotieren einer Graphen-Schicht (2), bei welchem die Graphen-Schicht (2) auf einem Trägersubstrat (1) abgeschieden, das Trägersubstrat (1) von der Graphen-Schicht in einer ersten Flüssigkeit (4) entfernt und die Graphen-Schicht (2) auf einen zu beschichtenden Oberflächenbereich eines Zielsubstrates (5) in einer zweiten Flüssigkeit (7) aufgetragen wird. Erfindungsgemäß wird ein Material (6) zum Dotieren der Graphen-Schicht (2) zumindest auf dem zu beschichtenden Oberflächenbereich des Zielsubstrates (5) abgeschieden, bevor die Graphen-Schicht (2) in der zweiten Flüssigkeit (7) auf den zu beschichtenden Oberflächenbereich des Zielsubstrates (5) aufgetragen wird.

Boron-doped diamond semiconductor

First and second synthetic diamond regions are doped with boron. The second synthetic diamond region is doped with boron to a greater degree than the first synthetic diamond region, and in physical contact with the first synthetic diamond region. In a further example embodiment, the first and second synthetic diamond regions form a diamond semiconductor, such as a Schottky diode when attached to at least one metallic lead.

High uniformity boron doped diamond material

The present invention relates to diamond material comprising a boron doped single crystal diamond substrate layer having a first surface and a boron doped single crystal diamond conductive layer on said first surface, wherein the distribution of boron in the conductive layer is more uniform than the distribution of boron in the substrate layer.

PLASMA ETCHING OF DIAMOND SURFACES

The present invention relates to a method of producing a diamond surface including the steps of providing an original diamond surface, subjecting the original diamond surface to plasma etching to remove at least 2 nm of material from the original surface and produce a plasma etched surface, the roughness Rq of the plasma etched surface at the location of the etched surface where the greatest depth of material has been removed satisfying at least one of the following conditions: Rq of the plasma etched surface is less than 1.5 times the roughness of Rq of the original surface, or Rq of the plasma etched surface is less than 1 nm.

Photo resist (PR) profile control

One or more techniques or systems for controlling a profile for photo resist (PR) are provided herein. In some embodiments, a first shield layer is formed on a first PR layer and a second PR layer is formed on the first shield layer. A first window is formed within the second PR layer during a first exposure with a mask. A second window is formed within the first shield layer based on the first window. A third window is formed within the first PR layer during a second exposure without a mask. Because, the third window is formed while the first shield layer and the second PR layer are on the first PR layer, a profile associated with the first PR layer is controlled. Contamination during ion bombardment is mitigated due to the controlled profile.

HEAVILY DOPED REGION IN DOUBLE-DIFFUSED SOURCE MOSFET (LDMOS) TRANSISTOR AND A METHOD OF FABRICATING THE SAME

Verfahren zur Herstellung eines Diamanthalbleiters

Halbleitervorrichtung und Verfahren zu ihrer Herstellung

In einer Halbleitervorrichtung ist ein p-Bereich (2, 4) auf einem ersten n-Bereich (1) angeordnet. Ein zweiter n-Bereich (3) ist auf dem p-Bereich (2, 4) angeordnet und von dem ersten n-Bereich (1) durch den p-Bereich (2, 4) getrennt. Eine Gateelektrode (8) dient dazu, einen n-Kanal zwischen dem ersten und zweiten n-Bereich (1, 3) zu bilden. Eine erste Elektrode (6) ist elektrisch mit dem p-Bereich (4) und dem zweiten n-Bereich (3) verbunden. Eine zweite Elektrode (11) ist auf dem ersten n-Bereich so angeordnet, dass sie von dem p-Bereich (2) durch den ersten n-Bereich (1) getrennt ist und zumindest ein Teil von ihr in Kontakt mit dem ersten n-Bereich (1) ist. Die zweite Elektrode (11) besteht aus einem beliebigen Metall oder einer beliebigen Legierung und dient dazu, Löcher in den ersten n-Bereich (1) zu injizieren.

도핑을 제어하기 위한 장치 및 방법

... 방법 및 장치가 개시되고, 상기 장치는: 적어도 하나의 충전된 기판(3); 2차원 재료(5)의 채널; 및 적어도 하나의 플로팅 전극(floating electrode)(7A 내지 C)을 포함하고, 플로팅 전극은 적어도 하나의 충전된 기판에 인접한 제 1 영역(10A 내지 C), 2차원 재료의 채널에 인접한 제 2 영역(11A 내지 C) 및 제 1 영역과 제 2 영역 사이의 전도성 상호접속부(9A 내지 C)를 포함하고, 제 1 영역은 제 2 영역보다 크며 적어도 하나의 플로팅 전극은 2차원 재료의 채널 내의 도핑 레벨을 제어하도록 배열된다.

A SEMICONDUCTOR DEVICE

In a semiconductor device comprising a first semiconductor layer (4) doped by dopants assuming such deep energy levels in the semiconductor material of said layer that the majority thereof will not be thermally activated at working temperature a contact layer (11) is of a metal having a work function (φ) being for a n-type doping substantially as high as or higher than the electron affinity (χ) of the semiconductor material and for a p-type doping substantially as high as or lower than the sum of on one hand the band gap between the conduction band and the valence band and on the other the electron affinity of said semiconductor material. The device comprises an irradiation source adapted to emit radiation of an energy being high enough for activating said dopants and thereby controlling the barrier against charge transport between the contact layer and the semiconductor layer.

FIELD EFFECT TRANSISTOR USING PHOSPHORUS-DOPED GRAPHENE, PREPARING METHOD OF THE SAME, PHOSPHORUS-DOPED GRAPHENE, AND PREPARING METHOD OF THE SAME

공기 중에서도 안정한, 인(phosphorus)-도핑된 그래핀을 포함하는 채널층을 이용한 전계효과 트랜지스터, 그의 제조 방법, 인-도핑된 그래핀, 및 그의 제조 방법에 관한 것이다.

Semiconductor device and method for fabricating the same

Method for thermally processing a substrate and associated system

Method for manufacturing a display device with low temperature diamond coatings

A display device with multiple low temperature diamond coatings, including a substrate as a base; an anode layer residing on the diamond substrate for emitting holes; a hole drift layer that includes a doped diamond coating residing on the anode layer; an emissive layer for emitting light and residing on the hole drift layer. The display device also includes an electron transport layer that includes a doped diamond coating residing on the light emitting layer; a cathode layer, residing on the electron transport layer, for emitting electrons that will drift towards the light emitting layer; and a diamond coated encapsulation layer for sealing the display device from atmospheric moisture; wherein the multiple low temperature diamond coatings are all formed below 750° C. on the display device.

Diamond semiconductor element and process for producing the same

A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

Bipolar junction transistor having an integrated switchable short

The invention solves the problem of depressed SOA of a bipolar junction transistor (BJT) when operated in an open base configuration by integrating in the same semiconductor chip a switchable short between the base and the emitter of the BJT. The switchable short switches between a high resistive value when the collector voltage of the BJT is lower than the base voltage. and a lower resistive value when the collector voltage is higher than the voltage base to effectively lower the BJT current gain (hFE). The switchable short in one implementation of the invention is in the form of a MOSFET with its gate connected to the BJT collector. The invention further teaches disposing in the integrated circuit chip a junction diode with a breakdown voltage lower than the BVCBO of the BJT. The addition of the junction diode provides a measure of maintaining the effectiveness of the MOSFET as switchable short at a reduced size.

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

A semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode being in contact with a surface of the semiconductor layer. The semiconductor layer includes a drift layer that forms the surface of the semiconductor layer and a high-resistance layer that is formed on a surface layer portion of the drift layer and that has higher resistance than the drift layer. The high-resistance layer is formed by implanting impurity ions from the surface of the semiconductor layer and then undergoing annealing treatment at less than 1500° C. 1. A semiconductor device comprising:a semiconductor layer made of a wide bandgap semiconductor; anda Schottky electrode being in contact with a front surface of the semiconductor layer, the semiconductor layer including:a drift layer that forms the front surface of the semiconductor layer; anda high-resistance layer that is formed on a surface layer portion of the drift layer and that has resistance higher than the drift layer,the high-resistance layer being formed by implanting impurity ions from the front surface of the semiconductor layer and then performing annealing treatment at less than 1500° C.2. The semiconductor device according to claim 1 , the semiconductor device being obtained by applying a voltage greater than a reverse breakdown voltage between the semiconductor layer and the Schottky electrode after applying annealing treatment onto the high-resistance layer.3. The semiconductor device according to claim 1 , wherein the semiconductor layer is made of SiC claim 1 , and has the front surface consisting of a Si plane claim 1 , andpits that match a dislocation defect are not formed on the front surface consisting of the Si plane of the semiconductor layer.4. The semiconductor device according to claim 1 , wherein surface roughness Rms of a junction interface of the front surface of the semiconductor layer making a junction with the Schottky electrode is ...

Techniques for manufacturing devices

Techniques for manufacturing a device are disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for forming a solar cell. The method may comprise: implanting p-type dopants into a substrate via a blanket ion implantation process; implanting n-type dopants into the substrate via the blanket ion implantation process; and performing a first annealing process to form the p-type region and performing a second annealing process to form a second n-type region.

Systems and methods for forming diamond heterojunction junction devices

A method of forming a p-n junction device comprises providing a base layer including a p-type diamond. A monolayer or few layer of a transition metal dichalcogenide (TMDC) is disposed on at least a portion of the base layer so as to form a heterojunction therebetween. The TMDC monolayer is an n-type layer such that the heterojunction between the intrinsic and p-type diamond base layer and the n-type TMDC monolayer is a p-n junction.

Sulfur Doping Method for Graphene

The invention provides a sulfur doping method for graphene, which comprises the steps of: 1) providing graphene and placing the grapheme in a chemical vapor deposition reaction chamber; 2) employing an inert gas to perform ventilation and exhaust treatment in the reaction chamber; 3) introducing a sulfur source gas to perform sulfur doping on the graphene at 500-1050° C.; and 4) cooling the reaction chamber in a hydrogen and inert gas atmosphere. The present invention can perform sulfur doping on the graphene simply and efficiently, the economic cost is low, and large-scale production can be realized. Large area sulfur doping on graphene can be realized, and doping of graphene on an insulating substrate or metal substrate can be carried out directly. 1. A sulfur doping method for graphene , which at least comprises the following steps of:1) providing graphene and placing the grapheme in a chemical vapor deposition reaction chamber;2) employing an inert gas to perform ventilation and exhaust treatment in the reaction chamber;3) introducing a sulfur source gas to perform sulfur doping on the graphene at 500-1050° C.; and4) cooling the reaction chamber in a hydrogen and inert gas atmosphere.2. The sulfur doping method for graphene according to claim 1 , characterized in that: a metal substrate is taken as a carrier for the graphene to place in the reaction chamber claim 1 , after step 2) claim 1 , it also comprises a step of a) introducing hydrogen to the reaction chamber at 200˜400° C. claim 1 , so as to perform reduction on oxide of surface of the metal substrate.3. The sulfur doping method for graphene according to claim 2 , characterized in that: the hydrogen of step a) has an airflow range of 20˜100 sccm.4. The sulfur doping method for graphene according to claim 1 , characterized in that: in step 2) claim 1 , ventilation and exhaust time of the inert gas is 10˜30 min claim 1 , with an airflow range of 500˜5000 sccm.5. The sulfur doping method for graphene ...

ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THEREOF

An electronic device, includes: a graphene nanoribbon having a first graphene and a second graphene; a first electrode coupled to the first graphene; and a second electrode coupled to the second graphene, wherein the first graphene is terminated on an edge by a first terminal group and has a first polarity and the second graphene is terminated on an edge by a second terminal group different to the first terminal group and has a second polarity different from the first polarity. 1. An electronic device , comprising:a graphene nanoribbon having a first graphene and a second graphene;a first electrode coupled to the first graphene; anda second electrode coupled to the second graphene,wherein the first graphene is terminated on an edge by a first terminal group and has a first polarity andthe second graphene is terminated on an edge by a second terminal group different to the first terminal group and has a second polarity different from the first polarity.2. The electronic device according to claim 1 ,wherein the first polarity of the first graphene is n-type and the second polarity of the second graphene is p-type andelectron affinity of the first graphene is greater than electron affinity of the second graphene.3. The electronic device according to claim 1 ,wherein the first graphene and the second graphene include 2 to 43 carbon atoms in the short direction.4. The electronic device according to claim 1 ,{'sub': 2', '2', '3', '3', '2', '2', '3, 'wherein the combination of the first terminal group of the first graphene and the second terminal group of the second graphene is one selected from (F, H), (Cl, H), (F, OH), (Cl, OH), (F, NH), (Cl, NH), (F, CH), (Cl, CH), (H, NH), (OH, NH), (OH, CH), and (H, OH).'}5. The electronic device according to claim 1 ,wherein the graphene nanoribbon has a third graphene coupled between the first graphene and the second graphene andthe third graphene differs from the first graphene and the second graphene in at least one of a width in ...

METHODS AND APPARATUSES RELATED TO SHAPING WAFERS FABRICATED BY ION IMPLANTATION

The wafer fabrication technique uses an ion implantation process on the back side of the wafer to control the shape of the wafer. At least one first dopant is implanted into a front side of a wafer to dope the wafer. At least one second dopant is implanted into a back side of the wafer in a dopant profile to create a back side structure, where the back side structure controls a shape of the wafer. A blank wafer is provided that has an undoped front side and a form shaping back side structure on the back side. A doped wafer is provided that has a dopant implanted on the front side and a form shaping back side structure on the back side that least partially offsets the strain in the wafer induced by the front side dopant. 1. A blank wafer comprising:a front side and a back side;a dopant profile implanted into the back side for controlling the shape of the wafer.2. The blank wafer according to claim 1 , wherein the dopant profile is in at least one of a ring pattern claim 1 , a ribbed pattern claim 1 , a grid pattern claim 1 , a ring and ribbed pattern and a pattern of discrete areas.3. The blank wafer according to claim 1 , wherein the dopant profile comprises at least two dopants.4. The blank wafer according to claim 1 , wherein the dopant profile creates a back side structure.5. The blank wafer according to claim 4 , wherein the back side structure extends over less than the entire back side.6. The blank wafer according to claim 4 , wherein the back side structure is in a masked pattern.7. The blank wafer according to claim 1 , wherein the front side comprises an epitaxial layer.8. The blank wafer according to claim 1 , wherein the blank wafer has a warped shape.9. The blank wafer according to claim 1 , wherein the blank wafer has a non-planar shape.10. The blank wafer according to claim 4 , wherein the back side structure is selected based on strains induced by a subsequent front side doping.11. A blank wafer comprising:a front side configured to support an active ...

Semiconductor device

A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer.

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR

A semiconductor device of an embodiment includes an electrode; and a silicon carbide layer in contact with the electrode and including: a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the electrode, in contact with the electrode, and containing at least one oxygen atom bonded to four carbon atoms. 1. A semiconductor device comprising:an electrode; anda silicon carbide layer in contact with the electrode and including:a first silicon carbide region of n-type; anda second silicon carbide region disposed between the first silicon carbide region and the electrode, the second silicon carbide region being in contact with the electrode, and the second silicon carbide region containing at least one oxygen atom bonded to four carbon atoms.2. The semiconductor device according to claim 1 , wherein a maximum concentration of oxygen in the second silicon carbide region is 1×10cmor more and 1×10cmor less.3. The semiconductor device according to claim 1 , wherein a concentration distribution of oxygen in the electrode and the second silicon carbide region has a first peak claim 1 , and a distance between an interface between the electrode and the second silicon carbide region and the first peak is 50 nm or less.4. The semiconductor device according to claim 3 , wherein a concentration distribution of oxygen in the electrode and the second silicon carbide region has a second peak between the first peak and the first silicon carbide region.5. The semiconductor device according to claim 1 , wherein an n-type impurity concentration in the first silicon carbide region is 1×10cmor more and 1×10cmor less.6. The semiconductor device according to claim 1 , wherein among oxygen atoms contained in the second silicon carbide region claim 1 , a ratio of oxygen atoms each bonded to four carbon atoms is higher than a ratio of oxygen atoms each bonded to four silicon atoms.7. A semiconductor device comprising:a ...

Diamond Semiconductor System and Method

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. A method of fabricating diamond semiconductors , the method including the steps of:selecting a diamond material having a diamond lattice, forming a diamond layer on a silicon dioxide layer;introducing acceptor dopant atoms to the diamond lattice to create pathways;introducing substitutional dopant atoms to the diamond lattice through the pathways; andannealing the diamond lattice to remove the pathways;{'sup': 22', '3, 'wherein the introduction of the acceptor dopant atoms does not create a critical density of more than 10/cmof vacancies in the diamond layer.'}6. The method of claim 5 , wherein the diamond material is intrinsic diamond.7. The method of claim 5 , wherein the acceptor dopant atoms are introduced at 293 to 298 degrees Kelvin.8. The method of claim 5 , wherein the acceptor dopant claim 5 , atoms are boron.9. The method of claim 5 , wherein the amount of acceptor dopant atoms is between 5×10/cmand 5×10/cm.10. The method of claim 5 , wherein the substitutional dopant atoms are introduced at or below 78 degrees Kelvin.11. The method of claim 5 , wherein the substitutional dopant atoms are introduced at less than 500 keV.12. The method of claim 5 , wherein the substitutional dopant atoms are introduced at less than 140 keV and at a ...

Diamond Semiconductor System and Method

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. A method of fabricating diamond semiconductors , the method including the steps of:selecting a diamond material having a diamond lattice, forming a diamond layer on a silicon dioxide layer;introducing acceptor dopant atoms to the diamond lattice to create a plurality of temporary dopant pathways;introducing substitutional dopant atoms to the diamond lattice through at least a portion of the temporary dopant pathways; andannealing the diamond lattice to remove at least some of the temporary dopant pathways;{'sup': 22', '3, 'wherein the introduction of the acceptor dopant atoms does not create more than 10/cmof vacancies in the diamond layer.'}6. The method of claim 5 , wherein the diamond material is intrinsic diamond.7. The method of claim 5 , wherein the acceptor dopant atoms are introduced at 293 to 298 degrees Kelvin.8. The method of claim 5 , wherein the acceptor dopant atoms are boron.9. The method of claim 5 , wherein the amount of acceptor dopant atoms is between 5×10/cmand 5×10/cm.10. The method of claim 5 , wherein the substitutional dopant atoms are introduced at or below 78 degrees Kelvin.11. The method of claim 5 , wherein the substitutional dopant atoms are introduced at less than 500 keV.12. The method of claim 5 , wherein the ...

Perc solar cell capable of improving photoelectric conversion efficiency and preparation method thereof

A PERC solar cell capable of improving photoelectric conversion efficiency and a preparation method thereof are provided. The solar cell consecutively includes, from the bottom up, a rear silver electrode ( 1 ), a rear aluminum field ( 2 ), a rear silicon nitride film ( 3 ), a rear aluminum oxide film ( 4 ), P-type silicon ( 5 ), N-type silicon ( 6 ), a front silicon nitride film ( 7 ), and a front silver electrode ( 8 ). The rear aluminum field ( 2 ) is connected to the P-type silicon ( 5 ) via a rear aluminum strip ( 10 ). The P-type silicon ( 5 ) is a silicon wafer of the cell. The N-type silicon ( 6 ) is an N-type emitter formed by diffusion via the front surface of the silicon wafer. The front silicon nitride film ( 7 ) is deposited on the front surface of the silicon wafer. The rear aluminum oxide film ( 4 ) is deposited on the rear surface of the silicon wafer. The rear aluminum oxide film ( 3 ) is deposited after the front silicon nitride film ( 7 ) is deposited on the silicon wafer, and the rear surface of the silicon wafer is washed before depositing the rear aluminum oxide film ( 3 ). The cell can significantly improves passivation effect of the rear aluminum oxide film and improve the open-circuit voltage and short-circuit current of the cell, thereby increasing photoelectric conversion efficiency of the cell.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a semiconductor substrate having a main surface and a back surface, a drift region having a first conductivity type, a body region formed in the drift region and having a second conductivity type, a plurality of grooves passing through the body region from the main surface toward the back surface, a gate electrode formed in the plurality of grooves with a gate insulating film interposed therebetween, and an electric field relaxation layer provided below the plurality of grooves in the drift region and having a second conductivity type. The electric field relaxation layer continuously extends over the entire body region. 1. A semiconductor device comprising:a semiconductor substrate having a main surface and a back surface;a drift region provided in the semiconductor substrate so as to be in contact with the main surface, the drift region having a first conductivity type;a body region selectively provided in the drift region, the body region having a second conductivity type different from the first conductivity type;first and second grooves passing through the body region, the first and second grooves extending in a first direction in plan view and disposed in a spaced relationship from each other in a second direction perpendicular to the first direction;a first semiconductor region formed in the body region, the first semiconductor region disposed between the first groove and the second groove and having the second conductivity type;a second semiconductor region formed in the body region, the second semiconductor region disposed between the first groove and the first semiconductor region and having the first conductivity type;a third semiconductor region formed in the body region, the third semiconductor region disposed between the second groove and the first semiconductor region and having the first conductivity type;a fourth semiconductor region formed in the drift region, the fourth semiconductor region disposed below the first ...

Semiconductor device and a method of manufacturing the same

A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

THERMAL DIFFUSION DOPING OF DIAMOND

Boron-doped diamond and methods for making it are provided. The doped diamond is made using an ultra-thin film of heavily boron-doped silicon as a dopant carrying material in a low temperature thermal diffusion doping process. 1. Boron-doped diamond comprising: a layer of diamond comprising a doped region extending into the layer from a surface , the doped region comprising substitutional boron dopant atoms , wherein the concentration of substitutional boron dopant atoms at the surface is at least 1×10cmand the depth profile of the substitutional boron dopant atoms corresponds to a complimentary-error-function.2. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at the surface is at least 2×10cm.3. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at the surface is at least 2.2×10cm.4. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at a depth of 100 nm from the surface is no greater than 1×10cm.5. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at a depth of 100 nm from the surface is no greater than 1×10cm.6. The diamond of claim 1 , wherein the diamond is free of Si atoms at a depth of 5 nm or greater from the surface.7. The diamond of claim 1 , wherein the surface is free of graphitized diamond.8. The diamond of claim 1 , wherein the diamond is natural diamond.9. The diamond of claim 1 , wherein the diamond comprises type IIa diamond.10. The diamond of claim 1 , wherein the diamond is single-crystalline diamond.11. The diamond of claim 1 , wherein the diamond is single-crystalline diamond claim 1 , the concentration of substitutional boron dopant atoms at the surface is at least 2×10cm claim 1 , and the concentration of substitutional boron dopant atoms at a depth of 100 nm from the surface is no greater than 1×10cm.12. A method of making substitutionally boron-doped diamond claim 1 , the method comprising: ...

Silicon carbide semiconductor device and method for manufacturing same

A method includes steps of: preparing a silicon carbide substrate having a first surface and including a first impurity region having a first conductivity type; forming an adjustment film and a mask film, the adjustment film covering at least a portion of the first surface, the mask film having an opening pattern through which the adjustment film is at least partially exposed; forming a second impurity region having a second conductivity type in the first impurity region by implanting an impurity into the first surface through the adjustment film using the mask film as a mask; and removing at least a portion of the adjustment film; and forming a third impurity region having the first conductivity type in the second impurity region by implanting an impurity into the first surface using the mask film as a mask.

Production of multiple semiconductor devices using a semiconductor process

In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device.

PROCESS FOR FORMING HOMOEPITAXIAL TUNNEL BARRIERS WITH HYDROGENATED GRAPHENE-ON-GRAPHENE FOR ROOM TEMPERATURE ELECTRONIC DEVICE APPLICATIONS

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same material—graphene. 1. A method of making a homoepitaxial tunnel barrier with hydrogenated graphene-on-graphene , comprising:growing graphene by chemical vapor deposition via decomposition of methane in a copper foil enclosure;removing the copper foil by etching;transferring and stacking graphene layers on a substrate;defining graphene mesas utilizing deep-UV lithography and an etch mask with PMMA and oxygen plasma;rinsing in acetone and isopropyl alcohol and removing the etch mask;defining reference contacts and bond pads;depositing Ti/Au using electron beam deposition;encapsulating edges of the graphene layers utilizing deep-UV lithography and a MMA/PMMA mask;sputter-depositing SiN wherein the SiN is about 10 nm;hydrogenating the graphene; andforming the homoepitaxial tunnel barrier.2. The method of making a homoepitaxial tunnel barrier with hydrogenated graphene-on-graphene of wherein the step of transferring and stacking graphene layers on a substrate includes stacking 4 graphene layers and wherein after the step of hydrogenating a conductive channel is present in the layers.3. The method of making a homoepitaxial tunnel barrier with hydrogenated graphene-on-graphene of further including the step of:depositing FM contacts via E-beam lithography.4. A method of making a homoepitaxial tunnel barrier with hydrogenated graphene-on-graphene claim 2 , comprising:providing a multilayer stack of graphene having top layers and bottom layers;encapsulating edges of the graphene layers utilizing deep-UV lithography and a MMA/PMMA mask;sputter-depositing SiN wherein the SiN is about 10 nm;hydrogenating the top layers of graphene; andcreating a homoepitaxial tunnel barrier.5. A method of making a homoepitaxial tunnel barrier transport device with hydrogenated graphene-on-graphene claim 2 , comprising:growing a first monolayer graphene film;{' ...

DIAMOND SEMICONDUCTOR SYSTEM AND METHOD

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer. 118. -. (canceled)9. A method of fabricating contacts on diamond semiconductors , the method including the steps of:{'sup': '2', 'selecting a diamond semiconductor material having a surface, the diamond semiconductor material having n-type donor atoms and a diamond lattice, wherein between 0.16% and 0.30% of the n-type donor atoms contribute conduction electrons with mobility greater than 770 cm/Vs to the diamond lattice at 100 kPa and 300K;'}forming a carbide interface contact layer on the surface; andforming a metal layer on the interface contact layer.10. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is a degeneratively doped semiconductor layer.11. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is deposed via sputtering.12. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is deposed via vapor deposition.13. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is a transparent metal.14. The method of fabricating contacts on diamond semiconductors of claim 9 , further including the step of deposing the diamond material on a metal substrate.15. The method of fabricating contacts on diamond semiconductors of claim 9 , further including the step of annealing the diamond material.16. A diamond semiconductor formed according to the method of .17. A method of fabricating contacts on diamond semiconductors claim 9 , the method including the steps of:{'sup': '2', 'selecting a diamond semiconductor material having a surface, ...

DIAMOND SEMICONDUCTOR SYSTEM AND METHOD

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer. 18-. (canceled)9. A method of fabricating contacts on diamond semiconductors , the method including the steps of:introducing acceptor dopant atoms to a diamond material to form a plurality of pathways;introducing substitutional n-type donor atoms to the diamond material through the plurality of pathways to form a diamond semiconductor material;selecting a surface of the diamond semiconductor material;forming a carbide interface contact layer on the surface; andforming a metal layer on the interface contact layer.10. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is a degeneratively doped semiconductor layer.11. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is deposed via sputtering.12. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is deposed via vapor deposition.13. The method of fabricating contacts on diamond semiconductors of claim 9 , wherein the metal layer is a transparent metal.14. The method of fabricating contacts on diamond semiconductors of claim 9 , further including the step of deposing the diamond material on a metal substrate.15. The method of fabricating contacts on diamond semiconductors of claim 9 , further including the step of annealing the diamond material.16. A diamond semiconductor formed according to the method of .17. A method of fabricating contacts on diamond semiconductors claim 9 , the method including the steps of:selecting a diamond semiconductor material having a surface, the diamond semiconductor material having n-type donor ...

Diamond Semiconductor System and Method

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm 2 /Vs to the diamond lattice at 100 kPa and 300K, and wherein the n-type donor atoms are introduced to the lattice through ion tracks.

ROLL-TO-ROLL DOPING METHOD OF GRAPHENE FILM, AND DOPED GRAPHENE FILM

The present disclosure relates to roll-to-roll doping method of graphene film, and doped graphene film. 1. A doped graphene film , formed by a roll-to-roll doping method comprising;doping the graphene film by passing the graphene film through a doping solution containing a dopant or a dopant vapor using roll-to-roll process.2. The doped graphene film of claim 1 ,wherein the graphene film is doped with an organic dopant, an inorganic dopant or their combination.3. The doped graphene film of claim 1 ,wherein the dopant includes at least one selected from the group consisting of an ionic liquid, an ionic gas, an acidic compound, and an organic polymeric compound.4. The doped graphene film of claim 1 ,{'sub': 2', '4', '4', '2', '6', '2', '4', '3', '2', '4', '3', '3', '2', '2', '3', '2, 'wherein the dopant includes at least one selected from the group consisting of NOBF, NOBF, NOSbF, HCl, HPO, CHCOOH, HSO, HNO, PVDF, Nation, AuCl, SOCl, Br, CHNO, dichlorodicyanoquinone, oxone, dimyristoylphosphatidylinositol, and trifluoromethanesulfonimide.'}5. The doped graphene film of claim 1 ,wherein the graphene film includes a monolayer graphene or a multilayer graphene.6. The doped graphene film of claim 1 ,wherein the graphene film has a roll shape, a foil shape, a tube shape, a plate shape, a sheet shape or a wire shape.7. A device manufactured by using a doped graphene film of .8. A roll-to-roll doping apparatus of a graphene comprising:a first roller unit that forms a layered structure including a substrate-graphene film-first flexible substrate;a second roller unit that removes the substrate from the layered structure by immersing the layered structure provided by the first roller unit in an etching solution and transfers the graphene film on the first flexible substrate at the same time;third roller unit that transfers the graphene film transferred on the first flexible substrate on a second flexible substrate; anda fourth roller unit that dopes the graphene film by passing ...

Systems and methods for gap filling improvement

Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.

PHOTOELECTRIC CONVERSION DEVICE, METHOD OF MANUFACTURING THE SAME, AND CAMERA

A photoelectric conversion device has a silicon substrate which includes a first portion configured to perform photoelectric conversion, and a second portion which is arranged farther apart from a light receiving surface of the silicon substrate than the first portion and contains carbon. A first peak concentration as a carbon peak concentration in the second portion is not less than 1×10[atoms/cm] and not more than 1×10[atoms/cm], and a second peak concentration as an oxygen peak concentration in the second portion is not less than 1/1000 and not more than 1/10 of the first peak concentration. 1. A photoelectric conversion device that includes a silicon substrate ,wherein the silicon substrate includes a first portion configured to perform photoelectric conversion, and a second portion which is arranged farther apart from a light receiving surface of the silicon substrate than the first portion and contains carbon,{'sup': 18', '3', '20', '3, 'a first peak concentration as a carbon peak concentration in the second portion is not less than 1×10[atoms/cm] and not more than 1×10[atoms/cm], and'}a second peak concentration as an oxygen peak concentration in the second portion is not less than 1/1000 and not more than 1/10 of the first peak concentration.2. The device according to claim 1 , wherein the first portion is arranged between the second portion and the light receiving surface in a direction perpendicular to the light receiving surface.3. The device according to claim 1 , wherein the second portion is arranged so as to form a layer along the light receiving surface.4. The device according to claim 1 , wherein the second portion is arranged such that a distance from the light receiving surface falls within a range of 3 μm to 20 μm.5. The device according to claim 1 , wherein the second portion includes a first region with a carbon concentration of not less than 1×10[atoms/cm] claim 1 , and a dimension of the first region in a direction perpendicular to the light ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a substrate having a first conductive type. An epitaxial layer having a second conductive type is disposed on the substrate. A first buried layer of the second conductive type is disposed within a high side region of the substrate. A second buried layer of the second conductive type is disposed directly above the first buried layer of the second conductive type. A top surface of the first buried layer of the second conductive type and a top surface of the second buried layer of the second conductive type are apart from a top surface of the epitaxial layer by different distances. A dopant concentration of the first buried layer of the second conductive type is less than that of the second buried layer of the second conductive type. 1. A semiconductor device , comprising: a high side region;', 'a low side region separated from the high side region; and', 'a level shift region and an isolation region disposed between the high side region and the low side region, wherein the isolation region separates the level shift region from the high side region;, 'a substrate having a first conductive type, and comprisingan epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductive type, and the first conductive type is different from the second conductive type;a first buried layer of the second conductive type disposed in the high side region;a second buried layer of the second conductive type disposed over the first buried layer of the second conductive type;wherein a top surface of the first buried layer of the second conductive type and a top surface of the second buried layer of the second conductive type are apart from a top surface of the epitaxial layer by different distances respectively, and wherein a dopant concentration of the first buried layer of the second conductive type is lower than a dopant concentration of the second buried layer of the second conductive type.2. The semiconductor device as ...

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

The aim of the present invention is to provide a semiconductor device containing a graphene p-n vertical tunneling-junction diode by assessing the optical and electrical characteristics of a graphene p-n junction produced by varying the doping concentration. The semiconductor device includes first graphene of a first doping type, and second graphene of a second doping type different from the first doping type, which is arranged on the first graphene and is in contact therewith. 1. A semiconductor device comprising:first graphene having a first doping type; andsecond graphene of a second doping type different from the first doping type, disposed on the first graphene and in contact with the first graphene.2. The semiconductor device of claim 1 , wherein the first doping type is an n type and the second doping type is a p type.3. The semiconductor device of claim 2 , wherein the first graphene comprises a high resistive layer claim 2 , andthe high resistive layer is formed on a boundary surface between the first graphene and the second graphene.4. The semiconductor device of claim 2 , wherein a current flowing in response to a forward voltage applied to the semiconductor device is a first current claim 2 , anda current flowing in response to a reverse voltage applied to the semiconductor device is a second current, andthe first current is smaller than the second current.5. The semiconductor device of claim 1 , wherein each of the first graphene and the second graphene comprises a single layer.6. The semiconductor device of claim 1 , further comprising:a substrate provided below the first graphene; anda first electrode and a second electrode formed on the first graphene and the second graphene, respectively.7. A semiconductor device comprising a p-n diode claim 1 , wherein a current flowing in response to a forward voltage applied to the p-n diode is a first current claim 1 ,a current flowing in response to a reverse voltage applied to the p-n diode is a second current ...

SEMICONDUCTOR COMPONENT HAVING A SIC SEMICONDUCTOR BODY

A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width. 1. A semiconductor component , comprising:a SiC semiconductor body;a gate electrode structure extending from a first surface of the SiC semiconductor body into the SiC semiconductor body, the gate electrode structure having a conductive connection structure and at a bottom a structure width;a shielding region formed in the SiC semiconductor body along the bottom, the shielding region having a central section which has a lateral first width; anda contact formed between the conductive connection structure and the shielding region,wherein in at least one doping plane extending approximately parallel to the bottom, a dopant concentration in the central section deviates by not more than 10% from a maximum value of the dopant concentration in the shielding region in the doping plane,wherein the first width is less than the structure width and is at least 30% of the structure width.2. The semiconductor component of claim 1 , wherein the doping plane connects laterally adjacent local maximum values of vertical dopant distributions in the shielding region.3. The semiconductor component of claim 1 , wherein the first width is less than a difference between the structure width and twice an average distance between the doping plane and the bottom.4. The semiconductor component of claim 1 , wherein the gate electrode structure has a field dielectric claim 1 , ...

METHOD FOR MANUFACTURING TRANSISTOR ACCORDING TO SELECTIVE PRINTING OF DOPANT

The present invention relates to a method for manufacturing a transistor according selective printing of a dopant. For the manufacture of a transistor, a semiconductor layer is formed on a substrate, and a dopant layer is formed on the semiconductor layer. In the formation of the dopant layer, an inkjet printing is used to selectively print an n type dopant or a p type dopant. 1. A method for manufacturing a transistor according to selective printing of a dopant , the method comprising:forming a semiconductor layer on a substrate for manufacture of a transistor; andforming a dopant layer on the semiconductor layer,wherein the formation of the dopant layer includes selectively printing an n type dopant or a p type dopant by inkjet printing.2. The method as claimed in claim 1 , wherein the n type dopant comprises at least one selected from the group consisting of cesium fluoride (CsF) claim 1 , bis(ethylenedithio)-tetrathiafulvalence (BEDT-TTF) claim 1 , tetrathianaphthacene (TTN) claim 1 , bis(cyclopentadienyl)-cobalt(II) (CoCp) claim 1 , chromium with the anion of 1 claim 1 ,3 claim 1 ,4 claim 1 ,6 claim 1 ,7 claim 1 ,8-hexahydro-2H-pyrimido[1 claim 1 ,2-a]pyrimidine (hpp) (Cr(hpp)) claim 1 , tungsten with the anion of 1 claim 1 ,3 claim 1 ,4 claim 1 ,6 claim 1 ,7 claim 1 ,8-hexahydro-2H-pyrimido[1 claim 1 ,2-a]pyrimidine (hpp) (W(hpp)) claim 1 , pyronin B chloride claim 1 , acridine orange base [3 claim 1 ,6-bis(dimethylamino)acridine (AOB)] claim 1 , leuco bases like leuco crystal violet (LCV) claim 1 , (4-(1 claim 1 ,3-dimethyl-2 claim 1 ,3-dihydro-1H-benzoimidazol-2yl)phenyl)dimethylamine (nDMBI) claim 1 , and 2-(2-methoxyphenyl)-1 claim 1 ,3-dimethyl-1H-benzoimidazol-3-ium iodide (o-MeO-DMBI-I) claim 1 ,{'sub': 4', '2', '3', '3, 'wherein the p type dopant comprises at least one selected from the group consisting of 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F-TCNQ), 3,6-difluoro-2,5,7,7,8,8-hexacyanoquinodimethane (F—HCNQ), molybdenum trioxide (MoO), ...

Ion Beam Quality Control Using A Movable Mass Resolving Device

A system and method for optimizing a ribbon ion beam in a beam line implantation system is disclosed. The system includes a mass resolving apparatus having a resolving aperture, in which the resolving aperture may be moved in the X and Z directions. Additionally, a controller is able to manipulate the mass analyzer and quadrupole lenses so that the crossover point of desired ions can also be moved in the X and Z directions. By manipulating the crossover point and the resolving aperture, the parameters of the ribbon ion beam may be manipulated to achieve a desired result. Movement of the crossover point in the X direction may affect the mean horizontal angle of the beamlets, while movement of the crossover point in the Z direction may affect the horizontal angular spread and beam current. 1. A beam line ion implantation system , comprising:an ion source;a quadrupole lens;a mass analyzer, wherein ions of a desired species exiting the mass analyzer cross at a crossover point;a collimator disposed after the crossover point; anda mass resolving device, having a resolving aperture, disposed between the mass analyzer and the collimator;wherein the mass resolving device is movable in a Z direction, the Z direction defined as a central trajectory of the ions travelling between the mass analyzer and the collimator.2. The beam line ion implantation system of claim 1 , wherein the mass resolving device is movable in an X direction claim 1 , the X direction defined as a direction of a width of the resolving aperture claim 1 , such that a center of the resolving aperture moves in the X direction.3. The beam line ion implantation system of claim 2 , wherein the width of the resolving aperture is adjustable claim 2 , and the width of the resolving aperture is adjusted independent of movement of the center of the resolving aperture.4. The beam line ion implantation system of claim 3 , wherein the mass resolving device comprises a first portion and a second portion claim 3 , which ...

Systems and Methods for Gap Filling Improvement

Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening. 1. A semiconductor structure comprising:a recess in a semiconductor substrate defining sidewalls and a bottom;a first conductive layer disposed along the sidewalls of the recess and defining a void, the first conductive layer having a first ion implantation density in a top portion distal from a bottom portion disposed proximate to the bottom of the recess, the bottom portion having a second ion density; anda second conductive layer disposed within the void.2. The semiconductor structure of claim 1 , further comprising a glue layer between the sidewalls and the first conductive layer claim 1 , the glue layer including titanium.3. The semiconductor structure of claim 1 , wherein the first ion density and the second ion density include helium ions.4. The semiconductor structure of claim 1 , wherein the first ion density and the second ion density include nitrogen ions.5. The semiconductor structure of claim 1 , wherein the first ion density and the second ion density include fluoride ions.6. The semiconductor structure of claim 1 , wherein a contact structure is disposed within the recess and the first conductive layer comprises cobalt and the second conducive ...

Photodetector having a tunable junction region doping profile configured to improve contact resistance performance

Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor material that includes a first type of majority carrier. A doping enhancement layer is formed over a region of the semiconductor material, wherein the doping enhancement layer includes a first type of material. A dopant is accelerated sufficiently to drive the dopant through the doping enhancement layer into the region of the semiconductor material. Accelerating the dopant through the doping enhancement layer also drives some of the first type of material from the doping enhancement layer into the region of the semiconductor material. The dopant within the region and the first type of material within the region contribute to the region having a second type of majority carrier.

Defects Annealing and Impurities Activation in Semiconductors at Thermodynamically Non-Stable Conditions

A symmetric multicycle rapid thermal annealing (SMRTA) method for annealing a semiconductor material without the material decomposing. The SMRTA method includes a first long-time annealing at a first temperature at which the material is thermodynamically stable, followed by multicycle rapid thermal annealing (MRTA) at temperatures at which the material is not thermodynamically stable, followed in turn by a second long-time annealing at a second temperature at which the material is thermodynamically stable. The SMRTA method can be used to form p-type and n-type semiconductor regions in doped III-nitride semiconductors, SiC, and diamond. 1. A process for annealing a semiconductor material without the material decomposing , the process including the steps of:(1) capping a semiconductor sample with a material that is thermodynamically stable at maximum annealing temperature;(2) positioning the capped semiconductor sample inside an enclosure;(3) charging the enclosure with one of an inert gas, nitrogen, hydrogen, and mixtures thereof at an applied gas pressure above one atmosphere; and{'sub': conv1', 'S', 'conv1', 'S', 'conv1, '(4) subjecting the capped semiconductor sample to a temperature Tlower than temperature Tfor a predetermined time period tTbeing a temperature above which the semiconductor sample becomes thermodynamically unstable at the applied gas pressure and tbeing at least several minutes or longer;'}{'sub': 'cov1', 'claim-text': [{'sub': max', 'S', 'max', 'S, '(a) rapidly heating the sample for a duration of several seconds from a temperature Tstart to a predetermined temperature T, Tstart being lower than Tand Tbeing higher than T;'}, {'sub': end', 'end', 'S, '(b) rapidly cooling the sample to a temperature Tfor a duration of several seconds, Tbeing just lower than T; and'}, {'sub': end', 'hold', 'hold, 'claim-text': [{'sub': S', 'max', 'pulse', 'pulse', 'd, 'wherein during each heating and cooling cycle the sample is exposed to temperatures within a ...

GRAPHENE TRANSISTOR AND TERNARY LOGIC DEVICE USING THE SAME

Disclosed is a graphene transistor using graphene as a channel region and a logic device using the same. A doping metal layer is provided over a graphene channel of the graphene transistor. The doping metal layer has a work function higher or lower than that of the graphene. When the doping metal layer has a work function lower than that of the graphene, the graphene, which is below the doping metal layer, is doped with an n-type. Also, when the doping metal layer has a work function higher than that of the graphene, the graphene, which is below the doping metal layer, is doped with a p-type. As described above, various aspects of junction may be implemented in the graphene channel, and three states may be obtained from a single transistor. 1. A graphene transistor comprising:a gate electrode having conductivity;a dielectric layer formed on the gate electrode;a graphene channel having a single-layer graphene formed on the dielectric layer;a source electrode and a drain electrode respectively formed at both end portions of the graphene channel based thereon and on the dielectric layer;a doping metal layer formed at a selected region of the graphene channel and configured to dope the graphene channel, which is below the doping metal layer, with a predetermined conductive type; anda passivation layer formed on the graphene channel and configured to shield the graphene channel and the doping metal layer,wherein the graphene channel includes:a doped graphene region disposed below the doping metal layer and having the predetermined conductive type;a first graphene region formed at one side of the doped graphene region and having a Fermi level different from that of the doped graphene region; anda second graphene region opposite to the first graphene region based on the doped graphene region and having a Fermi level different from that of the doped graphene region.2. The graphene transistor of claim 1 , wherein a work function of the doping metal layer has a value lower ...

METHOD FOR MANUFACTURING SILICON-CARBIDE SEMICONDUCTOR ELEMENT

In this method for manufacturing a semiconductor element, a modified layer produced by subjecting a substrate () to mechanical polishing is removed by heating the substrate () under Si vapor pressure. An epitaxial layer formation step, an ion implantation step, an ion activation step, and a second removal step are then performed. In the second removal step, macro-step bunching and insufficient ion-implanted portions of the surface of the substrate () performed the ion activation step are removed by heating the substrate () under Si vapor pressure. After that, an electrode formation step in which electrodes are formed on the substrate () is performed. 1. A method for treating a surface of a substrate having an off angle , a surface of the substrate being SiC , the method comprising:forming a modified layer in the substrate by applying pressure to the substrate;a first removal step of removing the modified layer by heating the substrate under Si vapor pressure and performing isotropic etching based upon etching rate to reciprocal of heating temperature.2. A method for treating a surface of a substrate having an off angle , a surface of the substrate being SiC , the method comprising:forming a modified layer in the substrate by applying pressure to the substrate;a first removal step of removing the modified layer by heating the substrate under Si vapor pressure at an etching rate of 35 nm/min or more.3. The method for treating the surface of the substrate according to claim 1 , whereinthe first removal step is performed at an etching rate of 35 nm/min or more.4. The method for treating the surface of the substrate according to claim 1 , whereinthe first removal step is performed at the etching rate of about 100 nm/min or more.5. The method for treating the surface of the substrate according to claim 2 , whereinthe first removal step is performed at the etching rate of about 100 nm/min or more.6. The method for treating the surface of the substrate according to claim 1 ...

DIAMOND SEMICONDUCTOR SYSTEM AND METHOD

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm/Vs to the diamond lattice at 100 kPa and 300K, and wherein the n-type donor atoms are introduced to the lattice through ion tracks. 1. A method of fabricating a monolithically integrated diamond semiconductor , the method including the steps of:seeding the surface of a substrate material;forming a diamond layer upon the surface of the substrate material; andforming a semiconductor layer within the diamond layer,{'sup': '2', 'wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the n-type donor atoms contribute conduction electrons with mobility greater than 770 cm/Vs to the diamond lattice at 100 kPa and 300K, and wherein the re-type donor atoms are introduced to the lattice through ion tracks, wherein the ion tracks are created using p-type acceptor dopant atoms.'}2. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the substrate material is selected from the group consisting of silicon claim 1 , silicon oxide claim 1 , refractory metal claim 1 , glass claim 1 , and wide band gap semiconductor material.3. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the diamond layer is formed using chemical vapor deposition.4. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the diamond layer is formed at or below 450 degrees Celsius.5. A monolithically ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Some embodiments of the disclosure provide a method for forming a semiconductor device. The method includes: forming a plurality of semiconductor material layers on a doped substrate; removing a part of the plurality of semiconductor material layers to form an exposed doped substrate; and ion implanting a dopant into the exposed doped substrate to form a doped semiconductor structure, where the doped substrate and the doped semiconductor structure have different polarities. 1. A method for forming a semiconductor device , comprising:forming a plurality of semiconductor material layers on a doped substrate;removing a part of the plurality of semiconductor material layers to form an exposed doped substrate; andion implanting a dopant into the exposed doped substrate to form a doped semiconductor structure, whereinthe doped substrate and the doped semiconductor structure have different polarities.2. The method according to claim 1 , wherein the doped substrate is a doped silicon substrate.3. The method according to claim 1 , wherein the doped substrate comprises a p-type semiconductor material and the doped semiconductor structure comprises an n-type semiconductor material.4. The method according to claim 3 , further comprising:ion implanting the n-type semiconductor material with a first doping concentration into the exposed doped substrate to form a first doped semiconductor structure of the doped semiconductor structure.5. The method according to claim 4 , wherein the n-type semiconductor material with the first doping concentration is ion implanted obliquely into the exposed doped substrate.6. The method according to claim 5 , wherein the n-type semiconductor material with the first doping concentration is ion implanted obliquely into the exposed doped substrate at multiple angles.7. The method according to claim 4 , wherein the first doped semiconductor structure has a doping concentration of about 10cmto about 10cm.8. The method according to claim 4 , further ...

METHOD OF FABRICATING ELECTRICALLY ISOLATED DIAMOND NANOWIRES AND ITS APPLICATION FOR NANOWIRE MOSFET

A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the dielectric or the polymer, etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire, depositing a metal layer to conformably cover the first portion of the diamond nanowire, and implanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond substrate, wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire. 1. A method for fabricating an electrically isolated diamond nanowire comprising:forming a diamond nanowire on a diamond substrate;depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate;planarizing the dielectric or the polymer;etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire;depositing a metal layer to conformably cover the first portion of the diamond nanowire; andimplanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond substrate;wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire.2. The method of further comprising:removing the dielectric or polymer before implanting ions.3. The method of further comprising:depositing by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), a second dielectric on the diamond nanowire to protect a surface of the diamond nanowire before depositing the dielectric or the polymer on the diamond nanowire and on the diamond substrate.4. The method of further ...

METHOD OF FABRICATING ELECTRICALLY ISOLATED DIAMOND NANOWIRES AND ITS APPLICATION FOR NANOWIRE MOSFET

A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the dielectric or the polymer, etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire, depositing a metal layer to conformably cover the first portion of the diamond nanowire, and implanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond substrate, wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire. 114-. (canceled)15. An electrically isolated diamond nanowire comprising:a diamond substrate;a diamond nanowire on the diamond substrate; anda plurality of ions implanted in the diamond nanowire below a top portion of the diamond nanowire, or at an intersection of the diamond nanowire and the diamond substrate.16. The electrically isolated diamond nanowire of :{'sub': '2', 'wherein the plurality of ions comprise N.'}17. The electrically isolated diamond nanowire of :wherein the plurality of ions are implanted at an oblique angle from a first side of the diamond nanowire.18. The electrically isolated diamond nanowire of :wherein the plurality of ions are implanted at an oblique angle from a second side of the diamond nanowire.19. A field effect transistor comprising:a diamond substrate;a channel on the diamond substrate, wherein the channel is a diamond nanowire; and 'wherein the plurality of ions are implanted at an oblique angle from a side of the diamond nanowire.', 'a plurality of ions implanted in the diamond nanowire below a top portion of the diamond nanowire, or at an intersection of the diamond nanowire and the diamond substrate;'}20. The field effect transistor of wherein the plurality of ions comprise N ...

FUNCTIONALIZED GRAPHENE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a functionalized graphene structure includes preparing a substrate having a graphene layer, forming an organic linker layer by providing an organic linker on the graphene layer, and forming a dopant layer by providing a dopant material including a metal on the organic linker layer. The organic linker layer and the dopant layer are formed in-situ. 1. A method for manufacturing a functionalized graphene structure , the method comprising:preparing a substrate having a graphene layer;forming an organic linker layer by providing an organic linker on the graphene layer; andforming a dopant layer by providing a dopant material including a metal on the organic linker layer,wherein the organic linker layer and the dopant layer are formed in-situ.2. The method of claim 1 , wherein the graphene layer is functionalized by the organic linker layer such that the dopant layer is conformally formed on the graphene layer.3. The method of claim 1 , wherein the organic linker is an aromatic element having a thiol group and a hydroxyl group.4. The method of claim 3 , wherein the organic linker is 4-mercaptophenol (4MP).5. The method of claim 3 , wherein sulfur (S) included in the thiol group and oxygen (O) included in the hydroxyl group of the organic linker are combined with the metal included in the dopant layer.6. The method of claim 1 , wherein the substrate comprises: a first portion on which the graphene layer is provided; and a second portion on which the graphene layer is not provided claim 1 ,wherein the forming of the organic linker layer by providing the organic linker on the graphene layer comprises:forming the organic linker layer on the graphene layer and the second portion.7. The method of claim 6 , wherein the organic linker layer formed on the second portion is removed by a purge process before the dopant material is provided on the organic linker layer by an atomic layer deposition (ALD) process claim 6 , and the organic linker layer on the ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion. 1. A semiconductor device comprising:an active cell region;an edge termination region surrounding the active cell region; andan intermediate region located at an intermediate position between the active cell region and the edge termination region,wherein the active cell region has a trench gate type MOS structure on a top side thereof, and has a p-collector layer, an n-buffer layer on the p-collector layer and an n-drift layer on the n-buffer layer as a vertical structure on a bottom side thereof, and the n-buffer layer has a first buffer portion provided on a p-collector layer side, and a second buffer portion provided on an n-drift layer side, andwherein a peak impurity concentration of the first buffer portion is higher than a peak impurity concentration of the second buffer portion, and an impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than an impurity concentration gradient on the n-drift layer side of the first buffer portion.2. A semiconductor device comprising:an active cell region;an edge termination region ...

DISTRIBUTED CURRENT LOW-RESISTANCE DIAMOND OHMIC CONTACTS

In some embodiments, a semiconductor structure can include: a diamond substrate having a surface conductive layer; a heavily doped region formed in the diamond substrate; and a metal contact positioned over the conductive surface layer such that a first portion of the heavily doped region is covered by the metal contact and a second portion of the heavily doped region is not covered by the metal contact.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

An impurity of a second conductivity type is selectively doped in a surface of a semiconductor substrate of a first conductivity type to form doped regions. A portion of a surface of the doped regions is covered by a heat insulating film. At least a remaining portion of the surface of the doped regions is covered by an absorbing film and the doped regions are heated through the absorbing film, enabling an impurity region of the second conductivity type to be formed having two or more of the doped regions that have a same impurity concentration and differing carrier concentrations.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate having an upper surface layer of a second conduction type formed at an upper surface side, a drift layer of a first conduction type formed under the upper surface layer, a buffer layer of the first conduction type formed under the drift layer, and a lower surface layer of the second conduction type formed under the buffer layer, the buffer layer includes a plurality of upper buffer layers provided apart from each other, and a plurality of lower buffer layers provided apart from each other between the plurality of upper buffer layers and the lower surface layer, wherein the plurality of upper buffer layers are formed so that average impurity concentrations in first sections each extending from the upper end of one of the upper buffer layers to the next lower buffer layer are unified as a first concentration.

METHODS AND APPARATUSES RELATED TO SHAPING WAFERS FABRICATED BY ION IMPLANTATION

The wafer fabrication technique uses an ion implantation process on the back side of the wafer to control the shape of the wafer. At least one first dopant is implanted into a front side of a wafer to dope the wafer. At least one second dopant is implanted into a back side of the wafer in a dopant profile to create a back side structure, where the back side structure controls a shape of the wafer. A blank wafer is provided that has an undoped front side and a form shaping back side structure on the back side. A doped wafer is provided that has a dopant implanted on the front side and a form shaping back side structure on the back side that least partially offsets the strain in the wafer induced by the front side dopant. 1. A method of fabricating a wafer comprising:implanting a first dopant into a front side of the wafer in a first ion implantation process; andimplanting a second dopant into a back side of the wafer in a second ion implantation process, where a dopant profile of the second dopant is selected to create a back side structure that controls a shape of the wafer.2. The method according to claim 1 , wherein the first ion implantation process occurs before the second ion implantation process.3. The method according to claim 1 , wherein the second ion implantation process occurs before the first ion implantation process.4. The method according to claim 1 , wherein the dopant profile of the structure is the same as a dopant profile of the first dopant.5. The method according to claim 1 , further comprising performing the first ion implantation process under substantially the same conditions as the second ion implantation process.6. The method according to claim 1 , further comprising implanting the first dopant in a first pattern on the front side and implanting the second dopant in a second pattern on the back side.7. The method according to claim 6 , wherein the first pattern and the second pattern are the same.8. The method according to claim 6 , wherein ...

DIAMOND SEMICONDUCTOR SYSTEM AND METHOD

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm/Vs to the diamond lattice at 100 kPa and 300K, and Wherein the n-type donor atoms are introduced to the lattice through ion tracks. 1. A method of fabricating a monolithically integrated diamond semiconductor , the method including the steps of:seeding the surface of a substrate material;forming a diamond layer upon the surface of the substrate material; andforming a semiconductor layer within the diamond layer,wherein the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the n-type donor atoms are introduced to the lattice through ion tracks, wherein the ion track are created using p-type acceptor dopant atoms.2. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the substrate material is selected from the group consisting of silicon claim 1 , silicon oxide claim 1 , refractory metal claim 1 , glass claim 1 , and wide band gap semiconductor material.3. The method of fabricating a monolithically integrated diamond semiconductor of claim 1 , wherein the diamond layer is formed using chemical vapor deposition.4. The method of lubricating a monolithically integrated diamond semiconductor of claim 1 , wherein the diamond layer is formed at or below 450 degrees Celsius.5. A monolithically integrated diamond semiconductor device formed according to the method of .6. The monolithically integrated diamond semiconductor device of claim 5 , wherein the device is one of a group consisting ...

THERMAL DIFFUSION DOPING OF DIAMOND

Boron-doped diamond and methods for making it are provided. The doped diamond is made using an ultra-thin film of heavily boron-doped silicon as a dopant carrying material in a low temperature thermal diffusion doping process. 1. A method of making substitutionally boron-doped diamond , the method comprising:bonding a flexible, boron-doped, single-crystalline silicon nanomembrane to the surface of a layer of diamond; andannealing the diamond and the boron-doped, single-crystalline silicon nanomembrane for a time sufficient to allow boron dopant atoms from the boron-doped, single-crystalline silicon nanomembrane to diffuse into the layer of diamond to form a doped region in the diamond.2. The method of claim 1 , wherein annealing the diamond and the boron-doped claim 1 , single-crystalline silicon nanomembrane comprises annealing the diamond and the boron-doped claim 1 , single-crystalline silicon nanomembrane at a temperature of at least 700° C.3. The method of claim 1 , wherein the concentration of boron dopant atoms at the surface of the layer of diamond after annealing is at least 1×10cm.4. The method of claim 1 , wherein the concentration of boron dopant atoms at the surface of the layer of diamond after annealing is at least 1×10cm.5. The method of claim 1 , wherein the concentration of boron dopant atoms at the surface of the layer of diamond after annealing is at least 2×10cm.6. The method of claim 1 , wherein the annealing temperature is no greater than about 1000° C.7. The method of claim 1 , wherein the boron dopant atom concentration in the boron-doped claim 1 , single-crystalline silicon nanomembrane is at least 1×10cmat the surface of the boron-doped claim 1 , single-crystalline silicon nanomembrane that is bonded to the surface of the layer of diamond.8. The method of claim 1 , wherein the boron dopant atom concentration in the boron-doped claim 1 , single-crystalline silicon nanomembrane is at least 1×10cmat the surface of the boron-doped claim 1 , ...

METHOD AND ARRANGEMENT FOR REDUCING CONTACT RESISTANCE OF TWO-DIMENSIONAL CRYSTAL MATERIAL

A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing. 1. A method , comprising:forming a contact material layer on a two-dimensional crystal material layer;performing ion implantation on at least the two-dimensional crystal material layer; andperforming thermal annealing of the contact material layer and the two-dimensional crystal material layer.2. The method according to claim 1 , wherein the ion implantation is performed via the contact material layer.3. The method according to claim 1 , wherein the ion implantation is performed prior to forming the contact material layer.4. The method according to claim 1 , wherein the two-dimensional crystal material layer is disposed on a substrate.5. The method according to claim 1 , further comprising patterning the contact material layer.6. The method according to claim 5 , wherein the patterning comprises:forming a patterned mask layer on the two-dimensional crystal material layer;forming a preliminary contact material layer on the two-dimensional crystal material layer with the mask layer formed thereon, wherein the ion implantation is performed via the preliminary contact material layer with the mask layer thereunder; andremoving the mask layer and portions of the preliminary contact material layer thereon, leaving remaining portions of the preliminary contact material layer to constitute the contact material layer which has been patterned.7. The method according to claim 6 , wherein the mask layer comprises photoresist claim 6 , and the removing is carried out by stripping off.8. The method according to claim 6 , wherein the mask layer comprises a hard mask claim 6 , and the removing is carried out by wet etching.9. The method according to claim 8 , further comprising performing thermal ...

AN APPARATUS AND METHOD FOR CONTROLLING DOPING

An apparatus and method, the apparatus comprising: at least one charged substrate (); a channel of two dimensional material (); and at least one floating electrode (A-C) wherein the floating electrode comprises a first area (A-C) adjacent the at least one charged substrate, a second area (A-C) adjacent the channel of two dimensional material and a conductive interconnection (A-C) between the first area and the second area wherein the first area is larger than the second area and wherein the at least one floating electrode is arranged to control the level of doping within the channel of two dimensional material. 1. An apparatus comprising:at least one charged substrate;a channel of two dimensional material; andat least one floating electrode wherein the floating electrode comprises a first area adjacent the at least one charged substrate, a second area adjacent the channel of two dimensional material and a conductive interconnection between the first area and the second area wherein the first area is larger than the second area and wherein the at least one floating electrode is arranged to control the level of doping within the channel of two dimensional material.2. An apparatus as claimed in comprising a plurality of floating electrodes.3. An apparatus as claimed in wherein different floating electrodes have at least one of; different first areas claim 2 , different second areas.4. An apparatus as claimed in claim 2 , wherein the different floating electrodes are provided adjacent to different portions of the channel of two dimensional material to enable different levels of doping to be provided in different portions of the channel of two dimensional material.5. An apparatus as claimed in claim 1 , wherein the doping within the two dimensional material is dependent upon an electric field provided by the second area of the floating electrode.6. An apparatus as claimed in claim 1 , wherein for each floating electrode a charged substrate and the first area of the ...

Chemical Sensors Based on Plasmon Resonance in Graphene

Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided. 1. A method of forming a graphene-based SPR sensor , comprising the steps of:depositing a dielectric layer on a conductive layer;patterning trenches at regular intervals in the dielectric layer to transform the dielectric layer into a corrugated surface having a series of grooves and ridges, wherein the grooves are formed by the trenches and the ridges are formed by the dielectric layer remaining between the trenches; anddepositing bulk graphene onto the corrugate surface of the dielectric layer, wherein the corrugated surface of the dielectric layer provides periodic regions of differing permittivity beneath the bulk graphene comprising i) first regions having a first permittivity to light and ii) second regions having a second permittivity to light.2. The method of claim 1 , wherein the trenches are patterned so as to extend only partway through the dielectric layer.3. The method of claim 2 , wherein a portion of the dielectric layer remaining at a bottom of the trenches has a thickness of at least about 5 nanometers.4. The method of ...

Implanted Dopant Activation for Wide Bandgap Semiconductor Electronics

An enhanced symmetric multicycle rapid thermal annealing process for removing defects and activating implanted dopant impurities in a III-nitride semiconductor sample. A sample is placed in an enclosure and heated to a temperature Tunder an applied pressure Pfor a time t. While the heating of the sample is maintained, the sample is subjected to a series of rapid laser irradiations under an applied pressure Pand a baseline temperature T. Each of the laser irradiations heats the sample to a temperature Tabove its thermodynamic stability limit. After a predetermined number of temperature pulses or a predetermined period of time, the laser irradiations are stopped and the sample is brought to a temperature Tand held at Tfor a time tto complete the annealing. 1. A method for removing defects and activating implanted dopant impurities in a wide bandgap semiconductor material sample , comprising:{'sub': '1', 'placing the sample into an enclosure under a first applied gas pressure P;'}{'sub': 1', '1', '1', '1', 's', '1, 'in a first annealing step, heating the sample to a first predetermined steady temperature Tand holding the sample at Tfor a first predetermined time tto begin removing the defects and activating the implanted dopant impurities in the sample, Tbeing a temperature below a temperature Tabove which the sample is thermodynamically unstable at pressure P;'}{'sub': 1', '2', '2', '2, 'after the expiration of time t, in a second annealing step, while maintaining the sample at a second predetermined temperature Tat a second applied gas pressure P, subjecting the sample to a plurality of laser irraditions having a predetermined power for one of a predetermined number of temperature pulses or a second predetermined time t,'}{'sub': max', 's, 'wherein each of the laser irradiations raises a temperature of an area of the sample impinged by the laser to a predetermined temperature T, higher than T,'}{'sub': s', 'p', 's', 'max, 'wherein at each laser irradiation, a ...

Edge termination structure for a power integrated device and corresponding manufacturing process

An integrated device has: a structural layer of semiconductor material doped with a first conductivity type and having a top surface defining a plane; a functional region, doped with a second conductivity type, arranged in an active area of the structural layer at the top surface, in the proximity of an edge area of the integrated device, which externally surrounds the active area; and an edge termination region, doped with the second conductivity type, joined to the functional region and arranged in the edge area. The edge termination region has a doping profile and a junction depth that vary in a first direction parallel to the plane.

Semiconductor device and method of manufacturing the same

A semiconductor device includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench formed in the n− type layer; a p type region disposed on both side surfaces of the first trench; an n+ type region disposed on both side surfaces of the first trench and disposed on the n− type layer and the p type region; a gate insulating layer disposed inside the first trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ region; and a drain electrode disposed on the second surface of the n+ type silicon carbide substrate, wherein a first channel as an accumulation layer channel and a second channel as an inversion layer channel are disposed in both side surfaces of the first trench, and the first channel and the second channel are disposed to be adjacent in a horizontal direction for the first surface of the n+ type silicon carbide substrate.

OPTOELECTRONIC SEMICONDUCTOR CHIP

An optoelectronic semiconductor chip including a semiconductor layer sequence containing a phosphide compound semiconductor material, wherein the semiconductor layer sequence includes a p-type semiconductor region, an n-type semiconductor region and an active layer disposed between the p-type semiconductor region and the n-type semiconductor region, a current spreading layer including a transparent conductive oxide adjoining the p-type semiconductor region, and a metallic p-connection layer at least regionally adjoining the current spreading layer, wherein the p-type semiconductor region includes a p-contact layer adjoining the current spreading layer, the p-contact layer contains GaP doped with C, a C dopant concentration in the p-contact layer is at least 5*10cm, and the p-contact layer is less than 100 nm thick. 113.-. (canceled)14. An optoelectronic semiconductor chip comprising:a semiconductor layer sequence comprising a phosphide compound semiconductor material, wherein the semiconductor layer sequence includes a p-type semiconductor region, an n-type semiconductor region and an active layer disposed between the p-type semiconductor region and the n-type semiconductor region,a current spreading layer comprising a transparent conductive oxide adjoining the p-type semiconductor region, anda metallic p-connection layer at least regionally adjoining the current spreading layer, whereinthe p-type semiconductor region comprises a p-contact layer adjoining the current spreading layer,the p-contact layer comprises GaP doped with C,{'sup': 19', '−3, 'a C dopant concentration in the p-contact layer is at least 5*10cm, and'}the p-contact layer is less than 100 nm thick.15. The optoelectronic semiconductor chip according to claim 14 , wherein the C dopant concentration in the p-contact layer is at least 1*10cm.16. The optoelectronic semiconductor chip according to claim 14 , wherein the p-contact layer has a thickness of 1 nm to 100 nm.17. The optoelectronic semiconductor ...

PERC solar cell capable of improving photoelectric conversion efficiency and its manufacturing method

method of forming channel layer in electric device and method of manufacturing electric device using the same

일 실시 예에 따르는 전기소자의 채널층 형성 방법이 개시된다. 먼저, 절연층을 상부에 구비하는 전도성 기판을 제공한다. 상기 전도성 기판과 도금 대상인 금속을 전극으로 사용하여 전해질 용액 내에서 전기도금을 실시한다. 이때, 상기 전도성 기판으로부터 상기 절연층을 통과하는 터널링 전류가 제공하는 전자와 상기 전해질 용액 내의 상기 금속의 이온이 결합함으로써 상기 절연층 상에 금속 채널층이 형성된다. Disclosed is a method of forming a channel layer of an electric device, according to an embodiment. First, a conductive substrate having an insulating layer thereon is provided. Electroplating is performed in an electrolyte solution using the conductive substrate and the metal to be plated as electrodes. In this case, a metal channel layer is formed on the insulating layer by combining electrons provided by the tunneling current passing through the insulating layer from the conductive substrate with ions of the metal in the electrolyte solution.

Organic Light Emitting Display device

PURPOSE: An organic light emitting display device is provided to secure a layout space by connecting the initial transistor with a adjacent pixel transistor and implementing a dual gate transistor. CONSTITUTION: In an organic light emitting display device, an organic electroluminescent display device includes a plurality of pixels. One pixel(100) includes a switching transistor, a driving transistor, a capacitor, an initial transistor, and an electro luminescence cell. A switching transistor(T11) delivers a data signal of a certain voltage level in response to a scanning signal, and a driving transistor(T12) generates a driving current according to the data signal of the certain voltage level through the switching transistor. A capacitor(C11) stores a data signal of a fixed voltage level delivered to a driving transistor, and the initial transistor(T14) discharge the data signal of voltage level stored in a capacitor in response to a previous scanning signal. An electro luminescence cell(EL11) radiates a light in response to a driving current through the driving transistor. The initial transistor of the pixel is connected with an initial transistor(T24) included in a adjacent pixel and the dual gate transistor is formed.

Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS

Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.

Oxide semiconductor substrate and schottky barrier diode

n 형 또는 p 형 실리콘 (Si) 기판과, 산화물 반도체층과, 쇼트키 전극층을 갖는 쇼트키 배리어 다이오드 소자로서, 상기 산화물 반도체층이 갈륨 (Ga) 을 주성분으로 하는 다결정 산화물 및 비정질 산화물 중 어느 일방 또는 양방을 함유하는 쇼트키 배리어 다이오드 소자. A Schottky barrier diode device having an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, wherein the oxide semiconductor layer contains gallium (Ga) as a main component, either of a polycrystalline oxide and an amorphous oxide Or a Schottky barrier diode element containing both.

Method for manufacturing a display device with low temperature diamond coatings

A display device with multiple low temperature diamond coatings, including a substrate as a base; an anode layer residing on the diamond substrate for emitting holes; a hole drift layer that includes a doped diamond coating residing on the anode layer; an emissive layer for emitting light and residing on the hole drift layer. The display device also includes an electron transport layer that includes a doped diamond coating residing on the light emitting layer; a cathode layer, residing on the electron transport layer, for emitting electrons that will drift towards the light emitting layer; and a diamond coated encapsulation layer for sealing the display device from atmospheric moisture; wherein the multiple low temperature diamond coatings are all formed below 750° C. on the display device.

Composition and method for selectively etching p-type doped polysilicon relative to silicon nitride

窒化ケイ素と比べてｐ型ドープポリシリコン（例えば、ホウ素ドープポリシリコン）を、該材料を上面に含むマイクロ電子デバイスから選択的に除去するための除去用組成物及び方法。基板は好ましくは、高誘電率／メタルゲート集積化スキームを備えたものである。 【選択図】なし

Fabrication method of n type semiconductor

PURPOSE: A method for manufacturing N-type semiconductor diamond is provided to be capable of manufacturing an N-type semiconductor diamond by etching the surface of diamond after Li compound and B compound are simultaneously doped using N-type impurity by means of chemical vapor deposition method. CONSTITUTION: A method for manufacturing N-type semiconductor diamond dopes Li compound being an n-type impurity and boron(B) compound being a p-type impurity on a diamond film at the same time when the diamond film is deposited using chemical vapor deposition method. B compound on the surface layer is removed by etching. Etching of the surface layer employs a hydrogen gas.

Organic light emitting diode and method for fabricating the same

본 발명은 인광 유기 발광다이오드 및 그 제조방법에 관한 것으로, 구체적으로는 기판상에 형성되는 애노드전극과 캐소드 전극을 포함하는 유기발광다이오드에 있어서, 기판상에 형성되는 애노드전극과 캐소드 전극을 포함하는 유기발광다이오드에 있어서, 순차로 형성되는 P-type 도펀트가 도핑된 제1 정공수송층(P-HTL)과 제2 정공수송층(HTL); 상기 제2 정공수송층상에 형성되는 적어도 1이상의 발광층(EML); 상기 발광층(EML)상에 순차로 형성되는 제1 전자수송층(ETL)과 N-type 도펀트가 도핑된 제2 전자수송층(N-ETL)을 포함하여 이루어지되, 상기 발광층(EML)의 구조를 양자우물구조로 형성하는 것을 특징으로 한다. 본 발명에 따르면, PIN 구조를 구비하는 인광 유기발광다이오드에 있어서, 전자주입 및 수송층과 발광층, 전공주입 및 수송층과 발광층을 동일한 유기재료를 사용하여 형성함으로써, 에너지 장벽으로 인한 특성감소를 줄일 수 있으며, 동일한 물질을 계속적으로 사용하기 때문에 공정이 간소해 지며, 제조단가가 낮아지는 효율성을 제공할 수 있는 효과가 있다. 인광, 유기 발광다이오드, 도펀트

TREATMENT METHOD FOR A DIAMOND SURFACE AND CORRESPONDING SURFACE

Organic Light Emitting Display

본 발명은 유기 전계 발광 표시 장치에 관한 것으로서, 해결하고자 하는 기술적 과제는 다음과 같다. 디멀티플렉서를 사용하여 알지비(RGB)데이터신호들을 인가하는 경우, 주사신호의 온(On)/오프(Off)에 관계없이 발광제어신호의 온(On) 기간동안 상기 알지비(RGB)데이터신호들을 인가함으로써 상기 알지비(RGB)데이터들이 화소 회로들의 각 용량성소자에 올바르게 저장될 수 있도록 하는데 있다. 이를 위하여 본 발명은 알지비(RGB) 데이터선들에 각각 전기적으로 연결되어, 상기 알지비(RGB) 데이터선들을 통하여 데이터전압를 인가하는 다수의 알지비(RGB)스위칭소자들을 갖는 디멀티플렉서와, 상기 디멀티플렉서의 알지비(RGB)스위칭소자들에 전기적으로 연결된 다수의 알지비(RGB)화소회로들을 포함하고, 상기 알지비(RGB) 화소회로들에 턴온의 발광제어신호가 인가되는 기간동안 상기 디멀티플렉서의 알지비(RGB)데이터전압이 인가됨을 특징으로 하는 유기 전계 발광 표시 장치를 개시한다. AMOLED, 유기전계발광소자, 디먹스, Demultiplexer, 유기전계발광표시장치 The present invention relates to an organic light emitting display device, and the technical problem to be solved is as follows. In the case of applying the RGB data signals using a demultiplexer, the RGB data signals are applied during the on period of the emission control signal regardless of the on / off of the scan signal. The RGB data can be correctly stored in each capacitive element of the pixel circuits. To this end, the present invention is a demultiplexer having a plurality of Algibi (RGB) switching elements that are electrically connected to each of the Algibi (RGB) data lines to apply a data voltage through the Algibi (RGB) data lines, and the demultiplexer of the demultiplexer A plurality of AlGV pixel circuits electrically connected to an RGB switching element, wherein an AlGV ratio of the demultiplexer is applied to the AlGV pixel circuits during a period in which a turn-on light emission control signal is applied; An organic light emitting display device is characterized in that a (RGB) data voltage is applied. AMOLED, Organic Light Emitting Device, Demux, Demultiplexer, Organic Light Emitting Display

TiO is adjusted using the Ti film of atomic layer depositionxThe method of stoichiometry

本发明涉及使用原子层沉积的Ti膜来调整TiO x 化学计量的方法。提供了亚化学计量的氧化钛的沉积并调整沉积的方法。方法涉及如下在室中的衬底上沉积高纯且共形的钛：(i)将衬底暴露至四碘化钛；(ii)清洗室；(iii)将衬底暴露至等离子体；(iv)清洗室；(v)重复(i)至(iv)，并处理衬底上沉积的钛来形成亚化学计量的氧化钛。氧化钛还可以在衬底上沉积钛之前来沉积。处理包含将衬底暴露至氧源和/或对衬底退火处理。

Diamond surface treatment method and corresponding diamond surface

(57)【要約】 本発明は、表面の処理方法および対応のダイヤモンド表面（５Ａ）に関する。該方法は、各々が少なくとも３つの正電荷を有するイオンを生成すること、および該イオンのビームをダイヤモンド表面へ放出することを包含し、その結果、イオンの効果下で少なくとも１つの表面領域を導電性にする。有利なことに、１５０ｎｍ未満の直径を有する導電性アイランド（６）がこのように形成され、これは次いで好ましくは電子のためのリザーバ（１０ｎｍ未満の直径を有する）として、または冷陰極をリパワーするためのリザーバとして使用される。本発明は、マイクロエレクトロニクスに適用可能であり、そして冷陰極を作製するためである。

Power semiconductor device for surpressing substrate recirculation current and mthod for fabricating the same

본 발명의 전력용 반도체 소자는, 트랜지스터가 형성되는 제1 영역과, 제어소자가 형성되는 제3 영역과, 그리고 상기 제1 영역과 제3 영역 사이의 격리를 위한 제2 영역을 포함한다. 이 소자는 제1 도전형의 기판과, 기판 위의 제2 도전형의 반도체영역을 포함하며, 기판과 반도체영역의 경계면에는 제2 도전형의 고농도 매몰층과 제1 도전형의 고농도 바닥층이 배치된다. 제1 영역에서 고농도 매몰층의 위아래에는 제1 도전형의 제1 고농도 바닥층이 배치되고, 이 구조는 제2 영역까지 일정 길이만큼 연장된다. 제2 영역에서는 제1 영역으로부터 연장된 고농도 바닥층 위로 제1 아이솔레이션영역이 배치되고, 고농도 매몰층 위로 제2 도전형의 고농도영역이 배치되며, 그리고 제1 도전형의 제2 고농도 바닥층 위로 제2 아이솔레이션영역이 배치된다. 이와 같은 구조에 따르면 제1 영역과 제2 영역에서의 기생 바이폴라 접합 트랜지스터를 제3 영역으로부터 전기적으로 분리시킬 수 있다.

Manufacturing method of transitor using selective print of dopant

본 발명은 도펀트의 선택적 인쇄에 따른 트랜지스터 제조방법에 관한 것으로 트랜지스터의 제조를 위해 기판 상에 반도체층을 형성하며, 상기 반도체층상에 도펀트를 형성하되, 상기 도펀트의 형성은 잉크젯 프린팅을 이용하여 n형 도펀트 또는 p형 도펀트를 선택적으로 인쇄하는 것을 특징으로 하는 트랜지스터 제조방법을 제공한다. The present invention relates to a method of manufacturing a transistor according to selective printing of a dopant, which method comprises forming a semiconductor layer on a substrate for the manufacture of a transistor, forming a dopant on the semiconductor layer, And selectively printing a dopant or a p-type dopant.

METHOD FOR TREATING A DIAMOND SURFACE AND CORRESPONDING DIAMOND SURFACE

The invention concerns a method for treating a surface and a corresponding diamond surface (5A). The method consists in producing ions each having at least three positive charges and in emitting a beam of said ions towards a diamond surface, so as to make at least one surface zone conductive under the effect of the ions. Advantageously, conductive islands (6) are thus formed having a diameter less than 150 nm, which are then preferably used as reservoir for an electron (having a diameter less than 10 nm) or as reservoirs for re-powering cold cathodes. The invention is applicable to microelectronics and for making cold cathodes.

Method of manufacturing n-type semiconductor diamond, and n-type semiconductor diamond

A method of manufacturing n-type semiconductor diamond by the present invention is characterized in producing diamond incorporating Li and N by implanting Li ions into, so that 10 ppm thereof will be contained i n, single-crystal diamond incorporating 10 ppm or more N, or else, in doping single-crystal diamond with Li and N ions, by implanting the ions so that ion-implantation depths at which the post-implantation Li and N concentrations each are 10 ppm or more will overlap, and thereafter annealin g the diamond in a temperature range of from 800.degree.C or more to less than 1800.degree.C to electrically activate the Li and N and restore the diamond crystalline structure. In the present invention, n-type semiconductor diamond incorporates, from the surface of the crystal to the same depth, 10 ppm or more of each of Li and N, wherein its sheet resistance is 10 7 .OMEGA./~ or less.

Semiconductor device and method for manufacturing semiconductor device

具备：有源单元区域；边缘端接区域，其将该有源单元区域包围；以及中间区域，其处于这些区域的中间，该有源单元区域在上表面侧具有沟槽栅型的MOS构造，作为下表面侧的纵向构造，具有p集电极层、该p集电极层之上的n缓冲层、以及该n缓冲层之上的n漂移层，该n缓冲层具有：第1缓冲部分，其设置在该p集电极层侧；以及第2缓冲部分，其设置在该n漂移层侧，该第1缓冲部分的峰值杂质浓度比该第2缓冲部分的峰值杂质浓度高，该第2缓冲部分的该n漂移层侧的杂质浓度梯度比该第1缓冲部分的该n漂移层侧的杂质浓度梯度平缓。

Fabrication of electrically isolated diamond nanowires and applications

一种制造电隔离金刚石纳米线的方法包括：在金刚石衬底上形成金刚石纳米线；在所述金刚石纳米线和所述金刚石衬底上沉积电介质或聚合物；将所述电介质或所述聚合物平坦化；蚀刻平坦化的所述电介质或所述聚合物的一部分以暴露所述金刚石纳米线的第一部分；沉积金属层以适形地覆盖所述金刚石纳米线的所述第一部分；以及将离子注入所述金刚石纳米线的位于所述金刚石纳米线的所述第一部分与所述金刚石衬底之间的第二部分中、或者注入所述金刚石纳米线与所述金刚石衬底的相交部；其中，所述离子被从所述金刚石纳米线的第一侧以倾斜的角度注入。

Method of fabricating n-type semiconductor diamond, and semiconductor diamond

An n-type diamond epitaxial layer 20 is formed by processing a single-crystalline {100} diamond substrate 10 so as to form a {111} plane, and subsequently by causing diamond to epitaxially grow while n-doping the diamond {111} plane. Further, a combination of the n-type semiconductor diamond, p-type semiconductor diamond, and non-doped diamond, obtained in the above-described way, as well as the use of p-type single-crystalline {100} diamond substrate allow for a pn junction type, a pnp junction type, an npn junction type and a pin junction type semiconductor diamond to be obtained.

Optoelectronic semiconductor chip

Es wird ein optoelektronischer Halbleiterchip (20) beschrieben, umfassend eine Halbleiterschichtenfolge (10), die ein Phosphid-Verbindungshalbleitermaterial aufweist, wobei die Halbleiterschichtenfolge (10) einen p-Typ Halbleiterbereich (4) einen n-Typ Halbleiterbereich (2), und eine zwischen dem p-Typ Halbleiterbereich (4) und dem n-Typ Halbleiterbereich (2) angeordnete aktive Schicht (3) enthält. Weiterhin umfass der optoelektronische Halbleiterchip eine an den p-Typ Halbleiterbereich (4) angrenzende Stromaufweitungsschicht (8), die ein transparentes leitfähiges Oxid aufweist, und eine metallische p-Anschlussschicht (12), die zumindest bereichsweise an die Stromaufweitungsschicht (8) angrenzt. Der p-Typ Halbleiterbereich (4) weist eine p-Kontaktschicht (7) auf, die an die Stromaufweitungsschicht (8) angrenzt. Die p-Kontaktschicht (7) weist mit C dotiertes GaP auf, wobei die C-Dotierstoffkonzentration mindestens 5 * 10 19 cm -3 beträgt, und wobei die p-Kontaktschicht (7) weniger als 100 nm dick ist. An optoelectronic semiconductor chip (20) is described, comprising a semiconductor layer sequence (10) comprising a phosphide compound semiconductor material, the semiconductor layer sequence (10) a p-type semiconductor region (4) an n-type semiconductor region (2), and an intermediate containing the p-type semiconductor region (4) and the n-type semiconductor region (2) arranged active layer (3). Furthermore, the optoelectronic semiconductor chip comprises a current spreading layer (8) which adjoins the p-type semiconductor region (4), which has a transparent conductive oxide, and a metallic p-connection layer (12) which adjoins the current spreading layer (8) at least in regions. The p-type semiconductor region (4) has a p-contact layer (7) adjacent to the current spreading layer (8). The p-contact layer (7) has C doped with C, wherein the C-dopant concentration is at least 5 * 10 19 cm -3 , and wherein the p-contact layer (7) is less than 100 nm thick.

Organic light-emitting diode with two or less layers of different organic materials

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type between the first electrode and the second electrode, a plurality of second semiconductor regions of a second conductivity type selectively provided between the first semiconductor region and the second electrode, a third semiconductor region of the first conductivity type provided between each of the second semiconductor regions and the second electrode, an insulating film provided on the first semiconductor region in a location between adjacent second semiconductor regions, the second semiconductor regions, and the third semiconductor region; and a third electrode located over the insulating film, wherein a portion of the insulating film and the third electrode extend inwardly of the second semiconductor regions.

Semiconductor devices and the method that diamond p-type electric-conducting raceway groove is formed using abrupt heterojunction

本发明公开了一种半导体器件及利用突变异质结形成金刚石p型导电沟道的方法，涉及半导体器件的制作方法技术领域。所述方法包括：在衬底上形成高阻金刚石层；在所述高阻金刚石层的上表面形成具有受主特性的一层或多层异质单质或化合物，在所述金刚石与受主层的界面处形成一个异质结，在所述金刚石的一侧近结10nm‑20nm处形成二维空穴气，利用二维空穴气作为p型导电沟道。所述方法可使p型金刚石材料沟道内的载流子浓度和迁移率在0℃‑1000℃范围内保持稳定，进而实现金刚石器件在高温环境下正常工作。

N-type semiconductor diamond manufacturing method and semiconductor diamond

Light-emitting organic diode comprising not more than two layers of different organic materials

本发明的二极管包括：基于第一有机材料(O1)的层，该层在与阴极(7)接触的其区域(6)内n型掺杂；基于第二有机材料(O2)的层，该层在与阳极(1)接触的其区域(2)内p型掺杂；以及电致发光区域(4；4’)，所述电致发光区域结合在一个层内，接触另一层，且既非n型掺杂也非p型掺杂，由此使得可以获得特别低成本高性能的二极管。

Semiconductor device, method for manufacturing semiconductor device, inverter circuit, drive unit, vehicle and lift

【課題】コンタクト抵抗のばらつきが抑制された半導体装置を提供する。【解決手段】実施形態の半導体装置は、電極と、電極に接する炭化珪素層であって、ｎ型の第１の炭化珪素領域と、第１の炭化珪素領域と電極との間に位置し、電極に接し、４個の炭素原子と結合する１個の酸素原子を含む第２の炭化珪素領域と、を含む炭化珪素層と、を備える。【選択図】図１

N-type semiconductor diamond manufacturing method and semiconductor diamond

本発明は、ｎ型半導体ダイヤモンドの製造方法、ｎ型半導体ダイヤモンド、ｐｎ接合型半導体ダイヤモンド、ｐｎｐ接合型半導体ダイヤモンド、ｎｐｎ接合型半導体ダイヤモンド、及びｐｉｎ接合型半導体ダイヤモンドに関する。本発明において、ダイヤモンド｛１００｝単結晶基板（１０）を加工し、ダイヤモンド｛１１１｝面を形成後、ダイヤモンド｛１１１｝面上にｎ型ドーパントをドープしながらダイヤモンドをエピタキシャル成長させてｎ型ダイヤモンドエピタキシャル層（２０）を形成する。また、上記のようにして得られるｎ型半導体ダイヤモンドとｐ型半導体ダイヤモンド、及びノンドープダイヤモンドを組み合わせること、ｐ型半導体ダイヤモンド｛１００｝単結晶基板を用いること等により、ｐｎ接合型、ｐｎｐ接合型、ｎｐｎ接合型及びｐｉｎ接合型の半導体ダイヤモンドが得られる。 The present invention relates to a method for producing an n-type semiconductor diamond, an n-type semiconductor diamond, a pn junction type semiconductor diamond, a pnp junction type semiconductor diamond, an npn junction type semiconductor diamond, and a pin junction type semiconductor diamond. In the present invention, a diamond {100} single crystal substrate (10) is processed to form a diamond {111} plane, and then diamond is epitaxially grown on the diamond {111} plane while doping with an n-type dopant to produce an n-type diamond epitaxial. A layer (20) is formed. Further, by combining the n-type semiconductor diamond, p-type semiconductor diamond, and non-doped diamond obtained as described above, using a p-type semiconductor diamond {100} single crystal substrate, etc., a pn junction type, a pnp junction type, Semiconductor diamonds of npn junction type and pin junction type are obtained.

MOS gate power semiconductor device

모스 게이트 전력 반도체 소자가 개시된다. 모스 게이트 전력 반도체 소자는 게이트 금속 전극 및 게이트 버스 라인 중 하나 이상의 하부에 형성되고, 에미터 금속 전극에 전기적으로 연결되는 하나 이상의 P형 웰; 및 상기 P형 웰의 내부에 형성되고, 상기 게이트 금속 전극 및 상기 게이트 버스 라인 중 하나 이상에 전기적으로 연결되는 하나 이상의 N형 웰을 포함할 수 있다. 본 발명에 의하여, 과전류 발생에 따른 소자의 열화 및/또는 파괴를 억제할 수 있다. 반도체 소자, 전력 반도체, IGBT, MOSFET A MOS gate power semiconductor device is disclosed. The MOS gate power semiconductor device includes one or more P-type wells formed under one or more of the gate metal electrodes and the gate bus lines and electrically connected to the emitter metal electrodes; And at least one N-type well formed in the P-type well and electrically connected to at least one of the gate metal electrode and the gate bus line. According to the present invention, deterioration and / or destruction of the device due to overcurrent can be suppressed. Semiconductor Devices, Power Semiconductors, IGBTs, MOSFETs

3 Graphene Transistor and Ternary Logic Device using the same

Method for reducing contact resistance of two-dimensional crystal material

本发明提供了一种降低二维晶体材料接触电阻的方法，包括：提供衬底，所述衬底上具有二维晶体材料层；在所述二维晶体材料层上形成图案化的掩膜层；在掩膜层及二维晶体材料层上形成接触材料层；进行离子注入；去除掩膜层及其上的接触材料层；进行热退火工艺。本发明不需要额外增加掩膜版和刻蚀工艺，自对准实现二维晶体材料层接触电阻的调整，有效降低了二维晶体材料与接触材料的接触电阻。

Diamond doping

A method of producing a doped diamond, typically a boron doped diamond, is provided. The method involves multiple cold implantation/rapid annealing steps. A doped diamond can be produced containing a high concentration of dopant atoms.

Manufacturing method for diamond semiconductor device

A process of forming a semiconductor which allows n type doping to be applied to a diamond semiconductor layer is carried out so as to form a diamond semiconductor layer on a substrate, forming a layer of SiO 2 over the diamond semiconductor layer and forming a resist pattern (14) over the SiO 2 layer. Etching processing of the SiO 2 layer via the resist pattern is carried out. Then, the exposed diamond layer is subjected to doping process under the following conditions; N 2 =30 SCCM' , 1.33 Pa, 100° C., microwave 850 W (2.45 GHz), RF bias 0 W, pulse duty ratio 1:2, a pulse type supply being used for microwave irradiation. Damage to the material by this process imparts high density, doping to the diamond layer. High saturation doping is possible according to this process.

Method for reducing growth defects of silicon carbide epitaxial wafer and silicon carbide substrate

本发明涉及一种降低碳化硅外延生长缺陷的方法及碳化硅衬底，所述方法包括：步骤10：碳化硅衬底的注入面表面沉积500‑800nm的SiO 2 作为掩膜层，对刻蚀窗口下掩膜层进行刻蚀，完成刻蚀后，对光刻胶进行清洗；步骤20：对上一步获得的碳化硅衬底的所述注入面进行N元素的高温离子注入，形成高N区域；步骤30：完成N元素的高温离子注入后，使用酸性缓冲液进行清洗，洗去掩膜层，得到经过处理的碳化硅衬底，以其作为外延生长的基片。该方法可以阻止常规碳化硅衬底中BPD延伸扩展导致的外延生长堆垛层错(SF)的形成，提高外延生长的质量。

Method for manufacturing transistor according to selective printing of dopant

The present invention relates to a method for manufacturing a transistor according to selective printing of a dopant. The present invention provides a transistor manufacturing method characterized in that a semiconductor layer is formed on a substrate, in order to manufacture a transistor, a dopant is formed on the semiconductor layer, and formation of the dopant is conducted by selectively printing an n-type dopant or a p-type dopant using inkjet printing.

Producing a diamond semiconductor by implanting dopant using ion implantation

A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

Semiconductor device

Eine Halbleitervorrichtung weist ein Substrat auf, das eine obere Oberflächenschicht einer zweiten Leitungsart, die an einer oberen Oberflächenseite gebildet ist, eine Drift-Schicht einer ersten Leitungsart, die unter der oberen Oberflächenschicht gebildet ist, eine Pufferschicht der ersten Leitungsart, die unter der Drift-Schicht gebildet ist, und eine untere Oberflächenschicht der zweiten Leitungsart, die unter der Pufferschicht gebildet ist, aufweist, wobei die Pufferschicht eine Mehrzahl von oberen Pufferschichten, die getrennt voneinander vorgesehen sind, und eine Mehrzahl von unteren Pufferschichten, die getrennt voneinander zwischen der Mehrzahl von oberen Pufferschichten und der unteren Oberflächenschicht vorgesehen sind, aufweist, wobei die Mehrzahl von oberen Pufferschichten so ausgebildet ist, dass durchschnittliche Verunreinigungskonzentrationen in ersten Abschnitten, die sich alle von dem oberen Ende von einer der oberen Pufferschichten zu der nächsttieferen Pufferschicht erstrecken, als eine erste Konzentration angeglichen sind. A semiconductor device comprises a substrate having an upper surface layer of a second conductivity type formed on an upper surface side, a first conductivity type drift layer formed under the upper surface layer, a first conductivity type buffer layer buried under the drift layer. Layer, and a lower surface layer of the second conductivity type formed under the buffer layer, the buffer layer having a plurality of upper buffer layers provided separately from each other and a plurality of lower buffer layers separated from each other between the plurality of upper buffer layers and the lower surface layer are provided, wherein the plurality of upper buffer layers are formed so that average impurity concentrations in first portions, all from the upper end of one of the upper buffer layers to the next lower Pufferc not equal to a first concentration.

Forming ohmic electrodes on diamond semiconductor

Disclosed is a heat-resisting ohmic electrode 4 on diamond film 2. The arrangement includes a p-type semiconducting diamond film 2, a boron-doped diamond layer 3 provided on the semiconducting diamond film; and an electrode 4 made of p-type Si selectively formed on the boron-doped diamond layer; wherein the boron concentration in the boron-doped diamond layer is from 1.0 x 10<19> to 1.8 x 10<23> cm<-3>, and at least one element selected from a group of B, Al and Ga is doped in the electrode 4 with a concentration from 1.0 x 10<20> to 5.0 x 10<22> cm<-3>. The ohmic electrode on diamond film is applicable for electronic devices operative at high temperature. The other surface of a Si substrate 1 receives a bonded Cu electrode 5. <IMAGE>

Boron-doped nanocrystalline diamond

A conductive boron doped nanocrystalline diamond is described. The boron doped diamond has a conductivity which uses the boron in the crystals as a charge carrier. The diamond is particularly useful for electrochemical electrodes in oxidation-reduction reactions and decontamination of aqueous solutions.

Semiconductor device and method for manufacturing semiconductor device

アクティブセル領域と、該アクティブセル領域を囲むエッジターミネーション領域と、これらの領域の中間にある中間領域と、を備え、該アクティブセル領域は、上面側にトレンチゲート型のＭＯＳ構造を有し、下面側の縦構造として、ｐコレクタ層、該ｐコレクタ層の上のｎバッファ層、及び該ｎバッファ層の上のｎドリフト層とを有し、該ｎバッファ層は、該ｐコレクタ層側に設けられた第１バッファ部分と、該ｎドリフト層側に設けられた第２バッファ部分と、を有し、該第１バッファ部分のピーク不純物濃度は、該第２バッファ部分のピーク不純物濃度より高く、該第２バッファ部分の該ｎドリフト層側の不純物濃度勾配は該第１バッファ部分の該ｎドリフト層側の不純物濃度勾配よりゆるやかである。 An active cell region, an edge termination region surrounding the active cell region, and an intermediate region between these regions, the active cell region having a trench gate type MOS structure on the upper surface side, and a lower surface As a vertical structure on the side, a p collector layer, an n buffer layer on the p collector layer, and an n drift layer on the n buffer layer are provided, and the n buffer layer is provided on the p collector layer side. A first buffer portion and a second buffer portion provided on the n drift layer side, and the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, The impurity concentration gradient on the n drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n drift layer side of the first buffer portion.