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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 3907. Отображено 100.
01-03-2012 дата публикации

Methods of selectively forming a material

Номер: US20120052681A1
Автор: Eugene P. Marsh
Принадлежит: Micron Technology Inc

Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

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Номер записи: 1
15-03-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120064690A1
Автор: Takakazu Kiyomura, Toshiyuki Hirota
Принадлежит: Elpida Memory Inc

A method for manufacturing a semiconductor device includes at least forming a lower electrode made of titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide, in which at least the uppermost layer of the dielectric film is formed by an atomic layer deposition (ALD) method on the lower electrode, forming a first protective film on the dielectric film without exceeding the film forming temperature of the ALD method over 70° C., and forming an upper electrode made of a titanium nitride on the first protective film.

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Номер записи: 2
21-06-2012 дата публикации

Semiconductor Device And Method Of Manufacturing The Same

Номер: US20120153261A1
Автор: Hyun-gi Hong, Jun-Youn Kim, Su-hee Chae, Young-jo Tak
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.

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Номер записи: 3
19-07-2012 дата публикации

Lanthanide dielectric with controlled interfaces

Номер: US20120181662A1
Автор: Arup Bhattacharyya
Принадлежит: Micron Technology Inc

Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

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Номер записи: 4
23-08-2012 дата публикации

Method and apparatus of fabricating silicon carbide semiconductor device

Номер: US20120214309A1
Автор: Hiromu Shiomi, Keiji Wada, Mitsuru Shimazu, Satomi Itoh, Toru Hiyoshi, Yasuo Namikawa
Принадлежит: Sumitomo Electric Industries Ltd

A method of fabricating a SiC semiconductor device includes the steps of preparing a silicon carbide semiconductor including a first surface having impurities implanted at least partially, forming a second surface by dry etching the first surface of the silicon carbide semiconductor using gas including hydrogen gas, and forming an oxide film constituting the silicon carbide semiconductor device on the second surface.

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Номер записи: 5
27-09-2012 дата публикации

Method of manufacturing a base substrate for a semi-conductor on insulator type substrate

Номер: US20120244687A1
Автор: Frederic Allibert, Oleg Kononchuk
Принадлежит: Soitec SA

A method and system are provided for manufacturing a base substrate that is used in manufacturing semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.

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Номер записи: 6
04-10-2012 дата публикации

Silicon oxycarbide, growth method of silicon oxycarbide layer, semiconductor device and manufacture method for semiconductor device

Номер: US20120252227A1
Автор: Atsuo Shimizu, Hirofumi Watatani, Kengo Inoue, Shun-ichi Fukuyama, Tamotsu Owada
Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O 2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.

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Номер записи: 7
01-11-2012 дата публикации

Method of depositing gate dielectric, method of preparing mis capacitor, and mis capacitor

Номер: US20120273861A1
Автор: Chao Xia, Dawei He, Dawei Xu, Xinhong Cheng, Yuehui Yu, Zhaorui Song, Zhongjian Wang
Принадлежит: Shanghai Institute of Microsystem and Information Technology of CAS

The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogen-containing oxide layer thereon. Then, a high-k gate dielectric layer is grown on the nitrogen-containing oxide layer surface by a plasma-enhanced atomic layer deposition process, and the oxide layer converts during the gate dielectric layer growth process into a buffer layer of a dielectric constant higher than SiO 2 . Then, a metal electrode is formed on both an upper layer and a lower layer of the thus-formed semiconductor construction, so that a MIS capacitor is prepared. According to the present invention, the formation of the buffer layer enables the interface characteristics between semiconductor materials and high-k gate dielectric layers to be improved effectively, equivalent oxide thickness (EOT) to be reduced and electrical properties to be enhanced.

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Номер записи: 8
15-11-2012 дата публикации

Methods for Manufacturing High Dielectric Constant Films

Номер: US20120289052A1
Автор: Maitreyee Mahajani, Tatsuya E. Sato
Принадлежит: Applied Materials Inc

Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface.

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Номер записи: 9
21-03-2013 дата публикации

Surface treating method and film depositing method

Номер: US20130072029A1
Автор: Hiroyuki Hashimoto, Tatsuya Yamaguchi
Принадлежит: Tokyo Electron Ltd

A surface treating method for treating a surface of a substrate inside a process chamber includes the steps of generating an atmosphere containing no moisture in the process chamber, heating the substrate inside the atmosphere containing no moisture in the process chamber; and causing a reaction between the substrate and an adhesion accelerating agent by feeding the adhesion accelerating agent gas into the process chamber.

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Номер записи: 10
04-04-2013 дата публикации

Treatment method for reducing particles in dual damascene silicon nitride process

Номер: US20130084701A1
Автор: Duoyuan HOU, Jun Xu, Ke Wang, Meimei GU
Принадлежит: Shanghai Huali Microelectronics Corp

A treatment method for reducing particles in a Dual Damascene Silicon Nitride (DDSN) process, including the following steps: forming a seed layer of copper on a silicon wafer; depositing a deposition layer of copper to cover the seed layer of copper; planarizing the deposition layer of copper; providing the silicon wafer into a reaction chamber and performing a pre-treatment on a surface of the deposition layer of copper using NH 3 gas under a plasma condition so as to reduce copper oxide(CuO) to copper(Cu) formed on the deposition layer of copper; in the reaction chamber, generating an etching block layer on the deposition layer of copper using a DDSN deposition process; cleaning the reaction chamber using NF 3 gas; and directing N 2 O gas into the reaction chamber and removing the remaining hydrogen (H) and fluorine (F) in the reaction chamber using the N 2 O gas under the plasma condition.

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Номер записи: 11
02-05-2013 дата публикации

Method for fabricating oxides/semiconductor interfaces

Номер: US20130109199A1
Автор: Georgios Vellianitis
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

By depositing a layer of oxidizing metal on the semiconductor surface first and then depositing a layer of the high-k oxide material over the layer of oxidizing metal by an atomic layer deposition, a high-k metal oxide is formed at the interface between the semiconductor substrate and the high-k oxide and prevents formation of the undesirable low-k semiconductor oxide layer at the semiconductor/high-k oxide interface.

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Номер записи: 12
23-05-2013 дата публикации

METHOD OF MANUFACTURING NON-PHOTOSENSITIVE POLYIMIDE PASSIVATION LAYER

Номер: US20130130504A1
Автор: Guo Xiaobo
Принадлежит: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.

A method of manufacturing non-photosensitive polyimide passivation layer is disclosed. The method includes: spin-coating a non-photosensitive polyimide layer over a wafer and baking it; depositing a silicon dioxide thin film thereon; spin-coating a photoresist layer over the silicon dioxide thin film and baking it; exposing and developing the photoresist layer to form a photoresist pattern; etching the silicon dioxide thin film by using the photoresist pattern as a mask; removing the patterned photoresist layer; dry etching the non-photosensitive polyimide layer by using the patterned silicon dioxide thin film as a mask; removing the patterned silicon dioxide thin film; and curing to form a imidized polyimide passivation layer. The method addresses issues of the traditional non-photosensitive polyimide process, including aluminum corrosion by developer, tapered profile of non-photosensitive polyimide layer and generation of photoresist residues. 1. A method of manufacturing non-photosensitive polyimide passivation layer , the method comprising:a) providing a wafer on which a non-photosensitive polyimide passivation layer is to be formed;b) spin-coating a non-photosensitive polyimide layer over the wafer and baking it;c) depositing a silicon dioxide thin film over the non-photosensitive polyimide layer;d) spin-coating a photoresist layer over the silicon dioxide thin film and baking it;e) exposing and developing the photoresist layer to form a photoresist pattern;f) etching the silicon dioxide thin film by using the photoresist pattern as a mask to form a silicon dioxide pattern;g) removing the patterned photoresist layer;h) dry etching the non-photosensitive polyimide layer by using the silicon dioxide pattern as a mask to form a non-photosensitive polyimide pattern;i) removing the patterned silicon dioxide thin film; andj) forming an imidized polyimide passivation layer by curing the patterned non-photosensitive polyimide layer.2. The method according to claim 1 , ...

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Номер записи: 13
04-07-2013 дата публикации

METHODS AND APPARATUS FOR WETTING PRETREATMENT FOR THROUGH RESIST METAL PLATING

Номер: US20130171833A1
Автор: Blackman Brian, Buckalew Bryan L., Higley Doug, Mayer Steven T., Ponnuswamy Thomas A., Rash Robert
Принадлежит:

Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute. 1. An apparatus comprising:a degasser configured to remove one or more dissolved gasses from a pre-wetting fluid to produce a degassed pre-wetting fluid; a wafer holder configured to hold a wafer substrate and configured to rotate the wafer substrate,', 'a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and', 'a fluid inlet coupled to the degasser and configured to deliver the degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second; and, 'a process chamber including rotating the wafer substrate at a first rotation rate, and', 'forming a wetting layer on the wafer substrate at the sub-atmospheric pressure in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid from the degasser and admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute, the degassed pre-wetting fluid being in a liquid state, while rotating the wafer substrate at the first rotation rate., 'a controller including program ...

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Номер записи: 14
29-08-2013 дата публикации

Wafer process body, wafer processing member, wafer processing temporary adhesive material, and method for manufacturing thin wafer

Номер: US20130220687A1
Автор: Hideto Kato, Hiroyuki Yasuda, Masahiro Furuya, Michihiro Sugo, Shohei Tagami
Принадлежит: Shin Etsu Chemical Co Ltd

Disclosed is a wafer process body, a temporary adhesive layer is formed on a supporting body, and a wafer having a circuit-formed front surface and a to-be-processed back surface is stacked on the temporary adhesive layer, wherein the temporary adhesive layer is provided with a first temporary adhesive layer including a non-aromatic saturated hydrocarbon group-containing organopolysiloxane layer (A) which is adhered to the front surface of the wafer so as to be detachable and a second temporary adhesive layer comprised of a thermosetting-modified siloxane polymer layer (B) which is stacked on the first temporary adhesive layer and adhered to the supporting body so as to be detachable. Thus, temporary adhesion of a wafer with a supporting body may become easy, process conformity with the TSV formation process and with the wafer-back surface-wiring process may become high, and removal may be done easily, with high productivity.

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Номер записи: 15
12-09-2013 дата публикации

Perovskite oxide film and ferroelectric film using the same, ferroelectric device, and method for manufacturing perovskite oxide film

Номер: US20130234564A1
Автор: Hiro EINISHI, Hiroshi Funakubo, Minoru Kurosawa, Mutsuo Ishikawa, Takahisa Shiraishi, Yukio Sakashita
Принадлежит: Fujifilm Corp, Tokyo Institute of Technology NUC

A perovskite oxide film is formed on a substrate, in which the perovskite oxide film has an average film thickness of not less than 5 μm and includes a perovskite oxide represented by a general formula (P) given below: (K 1−w−x , A w , B x )(Nb 1−y−z , C y , D z )O 3 - - - (P), where: 0<w<1.0, 0≦x≦0.2, 0≦y<1.0, 0≦z≦0.2, 0<w+x<1.0, A is an A-site element having an ionic valence of 1 other than K, B is an A-site element, C is a B-site element having an ionic valence of 5, D is a B-site element, each of A to D is one kind or a plurality of kinds of metal elements.

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Номер записи: 16
26-09-2013 дата публикации

FILM EMBEDDING METHOD AND SEMICONDUCTOR DEVICE

Номер: US20130249062A1
Автор: OKUCHI Hisashi, Tomita Hiroshi, Yoshimizu Yasuhito
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A method of forming an embedded film comprises depositing a first layer on a second layer that is disposed on a substrate and includes a material different from materials included in the first layer, forming an aperture through the first layer and into the second layer, the aperture having a side surface that includes an exposed portion of the first layer and an exposed portion of the second layer, bringing a material that includes organic molecules into contact with the exposed portion of the first layer and the exposed portion of the second layer to form a monomolecular film that covers the side surface, and forming the embedded film in the aperture with a material having a high enough affinity to the monomolecular film to substantially fill the aperture. 1. A method of forming an embedded film , the method comprising:depositing a first layer on a second layer, the second layer being disposed above a substrate and including a material different from materials included in the first layer;forming an aperture through the first layer and into the second layer, the aperture having a side surface that includes an exposed portion of the first layer and an exposed portion of the second layer;covering the side surface of the aperture with a monomolecular film that contains a material that includes organic molecules; andembedding a material in the aperture so as to substantially fill the aperture and form the embedded film.2. The film embedding method of claim 1 , wherein said material embedded in the aperture has a high enough affinity to the self-assembled monolayer to cause the material to substantially fill the aperture.3. The film embedding method of claim 1 , wherein the monomolecular film is formed by subjecting the organic molecules and at least one of the exposed portion of the first layer and the exposed portion of the second layer to a silane coupling reaction.4. The film embedding method of claim 1 , wherein the monomolecular film is formed by forming one of ...

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Номер записи: 17
09-01-2014 дата публикации

METHOD AND APPARATUS OF FORMING CARBON FILM

Номер: US20140011368A1
Автор: MIZUNAGA Satoshi, OBU Tomoyuki, OTSUKA Takehiro
Принадлежит:

According to an embodiment of present disclosure, a method of forming a carbon film on a substrate to be processed is provided. The method includes loading a substrate to be processed with a carbon film formed thereon into a processing chamber of a film forming apparatus (Process ), and thermally decomposing a hydrocarbon-based carbon source gas in the processing chamber to form a carbon film on the substrate to be processed (Process ). In Process a film forming temperature of the carbon film is set to a temperature less than a thermal decomposition temperature of a simple substance of the hydrocarbon-based carbon source gas without plasma assistance, the hydrocarbon-based carbon source gas and a thermal decomposition temperature drop gas containing a halogen element are introduced into the processing chamber, and a non-plasma thermal CVD method is performed. 1. A method of forming a carbon film on a substrate to be processed , comprising:loading a substrate to be processed, on which a carbon film is formed, into a processing chamber of a film forming apparatus; andforming a carbon film on the substrate to be processed by thermally decomposing a hydrocarbon-based carbon source gas in the processing chamber,wherein, in forming the carbon film, a film forming temperature of the carbon film is set to a temperature less than a thermal decomposition temperature at which a simple substance of the hydrocarbon-based carbon source gas is thermally decomposed without plasma assistance, and a thermal decomposition temperature drop gas, the hydrocarbon-based carbon source gas and the thermal decomposition temperature drop gas containing a halogen element are introduced into the processing chamber, anda non-plasma thermal CVD method is performed in forming the carbon film on the substrate to be processed.2. The method of claim 1 , wherein the thermal decomposition temperature drop gas containing the halogen element is selected from gases containing at least one of fluorine (F) ...

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Номер записи: 18
13-02-2014 дата публикации

Organic light emitting diode display

Номер: US20140042403A1
Автор: Kyung-Chan Chae, Young-Mi Cho, Young-Sahn Lee
Принадлежит: Samsung Display Co Ltd

An organic light emitting diode display according to an exemplary embodiment includes a substrate, a pixel electrode on the substrate, an organic emission layer on the pixel electrode, a common electrode on the organic emission layer, a cover layer on the common electrode, an oxidation reducing layer on the cover layer, and a thin film encapsulation layer covering the oxidation reducing layer, the oxidation reducing layer being configured to reduce oxidation of the common electrode, the oxidation reducing layer being separated from the common electrode. The oxidation reducing layer may include at least one of a dummy common electrode, an ultraviolet ray (UV) blocking layer, and a buffer layer.

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Номер записи: 19
06-03-2014 дата публикации

Manufacturing method and manufacturing apparatus of functional element

Номер: US20140065765A1
Автор: Hiroshi Tomita, Hisashi Okuchi, Yasuhito Yoshimizu, Yusuke Tanaka
Принадлежит: Toshiba Corp

According to one embodiment, the manufacturing method of a functional element includes filling a solvent comprising hydrogen gas and having organic molecules dispersed therein into a gap between the first electrode and the second electrode formed facing the first electrode, and forming an organic layer containing the organic molecules mentioned above between the first electrode and the second electrode.

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Номер записи: 20
05-01-2017 дата публикации

Substrate processing method and recording medium

Номер: US20170004993A1
Автор: Keiichi Tanaka
Принадлежит: Tokyo Electron Ltd

Electric charging of a substrate caused by a friction between a fluid and a surface of the substrate being rotated can be suppressed. At least a part of a surface insulating layer (thermal oxide film) on a peripheral portion of a substrate W is removed, and an underlayer (silicon wafer) having higher conductivity than a material of the surface insulating layer is exposed. Then, a process is performed on the substrate while holding and rotating the substrate by a substrate holding device. Here, at least a portion of the substrate holding device which comes into contact with the underlayer is made of a conductive material. In performing the process on the substrate, an electric charge generated in the surface insulating layer of the substrate is removed via the underlayer and the substrate holding device.

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Номер записи: 21
04-01-2018 дата публикации

Combined reactive gas species for high-mobility channel passivation

Номер: US20180005821A1
Автор: John Rozen, Takashi Ando, Vijay Narayanan, Yohei Ogawa
Принадлежит: International Business Machines Corp, Ulvac Inc, Ulvac Technologies Inc

A technique relates to in-situ cleaning of a high-mobility substrate. Alternating pulses of a metal precursor and exposure to a plasma of a gas or gas mixture are applied. The gas or gas mixture contains both nitrogen and hydrogen (e.g., NH 3 ). A passivation layer is formed on the high-mobility substrate by alternating pulses of the metal precursor and exposure to the plasma of a gas, or gas mixture, containing both nitrogen and hydrogen.

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Номер записи: 22
07-01-2021 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20210005734A1
Автор: CHANG Chih-Sheng, DIAZ Carlos H., LU Chun-Chieh, PENG Cheng-Yi, Yeh Ling-Yen
Принадлежит:

In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer. 1. A semiconductor device , comprising:a fin structure including a channel region protruding from an isolation insulating layer;a ferroelectric dielectric layer disposed over the channel layer; anda conductive layer comprising a (111) oriented crystalline layer; anda gate electrode layer disposed over the conductive layer,wherein the first metallic layer includes a TiN layer doped with Si, and comprises a (111) oriented crystalline structure.2. The semiconductor device of claim 1 , wherein the ferroelectric dielectric layer includes a HfZrOlayer comprising a (111) oriented orthorhombic crystal.3. The semiconductor device of claim 2 , wherein the ferroelectric dielectric layer includes Ti in an amount of 2-5 mol %.4. The semiconductor device of claim 2 , wherein the ferroelectric dielectric layer includes Al in an amount of 5-7 mol %.5. The semiconductor device of claim 2 , wherein a thickness of the ferroelectric dielectric layer is in a range from 1.0 nm to 5 nm.6. A semiconductor device claim 2 , comprising:a channel layer made of a semiconductor;an interfacial layer disposed on the channel layer;a seed layer disposed on the interfacial layer.a ferroelectric dielectric layer disposed over the seed layer; anda gate electrode layer disposed over the ferroelectric dielectric layer,wherein the ferroelectric dielectric layer comprises a (111) oriented orthorhombic crystal.7. The semiconductor device of claim 6 , wherein the ferroelectric dielectric layer includes ...

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Номер записи: 23
02-01-2020 дата публикации

Using a self-assembly layer to facilitate selective formation of an etching stop layer

Номер: US20200006060A1
Автор: Cheng-Chin Lee, Hai-Ching Chen, Hsin-Yen Huang, Shao-Kuan Lee, Shau-Lin Shue, Yung-Hsu WU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

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Номер записи: 24
15-01-2015 дата публикации

In-situ deposition of film stacks

Номер: US20150013607A1
Автор: Bart J. van Schravendijk, Dong Niu, George Andrew Antonelli, Jason Dirk Haverkamp, Jennifer L. Petraglia, John B. Alexy, Joseph L. Womack, Keith Fox, Mandyam A. Sriram, Patrick G. Breiling, Pramod Subramonium
Принадлежит: Novellus Systems Inc

An apparatus for depositing film stacks in-situ (i.e., without a vacuum break or air exposure) are described. In one example, a plasma-enhanced chemical vapor deposition apparatus configured to deposit a plurality of film layers on a substrate without exposing the substrate to a vacuum break between film deposition phases, is provided. The apparatus includes a process chamber, a plasma source and a controller configured to control the plasma source to generate reactant radicals using a particular reactant gas mixture during the particular deposition phase, and sustain the plasma during a transition from the particular reactant gas mixture supplied during the particular deposition phase to a different reactant gas mixture supplied during a different deposition phase.

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Номер записи: 25
11-01-2018 дата публикации

KIT AND LAMINATE

Номер: US20180012751A1
Автор: IWAI Yu, KAMOCHI Yoshitaka, KOYAMA Ichiro, NAKAMURA Atsushi
Принадлежит: FUJIFILM Corporation

Provided are a kit and a laminate which are capable of suppressing residues derived from a temporary adhesive in manufacture of a semiconductor. The kit for manufacturing a semiconductor device includes a composition which contains a solvent A; a composition which contains a solvent B; and a composition which contains a solvent C, in which the kit is used when a temporary adhesive layer is formed on a first substrate using a temporary adhesive composition containing a temporary adhesive and the solvent A, at least some of an excessive amount of the temporary adhesive on the first substrate is washed using the composition containing the solvent B, a laminate is manufactured by bonding the first substrate and a second substrate through the temporary adhesive layer, one of the first substrate and the second substrate is peeled off from the laminate at a temperature of lower than 40° C., and then the temporary adhesive remaining on at least one of the first substrate or the second substrate is washed using the composition containing the solvent C, and the solvent A, the solvent B, and the solvent C respectively satisfy a predetermined vapor pressure and a predetermined saturated solubility. 1. A kit for manufacturing a semiconductor device comprising:a composition which contains a solvent A;a composition which contains a solvent B; anda composition which contains a solvent C,wherein the kit is used when a temporary adhesive layer is formed on a first substrate using a temporary adhesive composition containing a temporary adhesive and the solvent A, at least some of an excessive amount of the temporary adhesive on the first substrate is washed using the composition containing the solvent B, a laminate is manufactured by bonding the first substrate and a second substrate through the temporary adhesive layer, one of the first substrate and the second substrate is peeled off from the laminate at a temperature of lower than 40° C., and then the temporary adhesive remaining ...

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Номер записи: 26
10-01-2019 дата публикации

Silicon carbide mosfet device and method for manufacturing the same

Номер: US20190013383A1
Автор: Chengyue Yang, Chengzhan LI, Guoyou Liu, Huajun Shen, Jingtao ZHOU, Xinyu Liu, Yidan TANG, Yun Bai
Принадлежит: Institute of Microelectronics of CAS, Zhuzhou CRRC Times Electric Co Ltd

The present disclosure discloses a self-aligned silicon carbide MOSFET device with an optimized P+ region and a manufacturing method thereof. The self-aligned silicon carbide MOSFET device is formed by a plurality of silicon carbide MOSFET device cells connected in parallel, and these silicon carbide MOSFET device cells are arranged evenly. The silicon carbide MOSFET device cell comprises two source electrodes, one gate electrode, one gate oxide layer, two N+ source regions, two P+ contact regions, two P wells, one N- drift layer, one buffer layer, one N+ substrate, one drain electrode and one isolation dielectric layer. By optimizing the P+ region, the present disclosure forms a good source ohmic contact, reduces the on-resistance, and also shorts the source electrode and the P well to prevent the parasitic transistor effect of the parasitic NPN and PiN, which may take both conduction characteristics and the breakdown characteristics of the device into consideration, and may be applied to a high voltage, high frequency silicon carbide MOSFET device. The self-aligned manufacturing method used in the present disclosure simplifies the process, controls a size of a channel accurately, and may produce a lateral and vertical power MOSFET.

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Номер записи: 27
10-01-2019 дата публикации

INTERLAYER DIELECTRIC FOR NON-PLANAR TRANSISTORS

Номер: US20190013406A1
Автор: Luce Jeanne, Pradhan Sameer
Принадлежит: Intel Corporation

The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor. 111-. (canceled)12. An integrated circuit (IC) structure , comprising:a fin having a source and a drain;a transistor gate formed on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode;a capping structure over the gate electrode; anda dielectric layer adjacent the sidewalls, wherein an upper portion of the dielectric layer has a higher density than a lower portion of the dielectric layer.13. The integrated circuit (IC) structure of claim 12 , wherein the upper portion of the dielectric layer comprises an annealed portion of the dielectric layer.14. The integrated circuit (IC) structure of claim 12 , wherein the upper portion of the dielectric layer comprises an oxidized portion of the dielectric layer.15. The integrated circuit (IC) structure of claim 12 , wherein the upper portion of the dielectric layer comprises an annealed and oxidized portion of the dielectric layer.16. The integrated circuit (IC) structure of claim 12 , further comprising a contact extending through the dielectric layer to one of the source and the drain.17. The integrated circuit (IC) structure of claim 12 , wherein the fin comprises silicon.18. The integrated circuit (IC) structure of claim 12 , wherein the capping structure comprises silicon and nitrogen.19. The integrated circuit (IC) structure of claim 18 , wherein the capping structure comprises silicon nitride.20. The integrated circuit (IC) structure of claim 12 , wherein the ...

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Номер записи: 28
14-01-2021 дата публикации

Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium

Номер: US20210013032A1
Автор: Hiroto YAMAGISHI, Takeo Hanashima
Принадлежит: Kokusai Electric Corp

There is provided a technique that includes: forming an initial oxide layer on a surface of a substrate by performing a set m times (where m is an integer equal to or greater than 1), the set including non-simultaneously performing: (a) oxidizing the surface of the substrate under a condition that an oxidation amount of the substrate increases from an upstream side to a downstream side of a gas flow by supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate; and (b) oxidizing the surface of the substrate under a condition that the oxidation amount of the substrate decreases from the upstream side to the downstream side of the gas flow by supplying the oxygen-containing gas and the hydrogen-containing gas to the substrate; and forming a film on the initial oxide layer by supplying a precursor gas to the substrate.

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Номер записи: 29
14-01-2021 дата публикации

METHODS FOR MAKING EUV PATTERNABLE HARD MASKS

Номер: US20210013034A1
Автор: Nardi Katie Lynn, Weidman Timothy William, Wu Chenghao
Принадлежит: LAM RESEARCH CORPORATION

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant so as to form a polymerized organometallic material; and depositing the organometallic polymer-like material onto the surface of the semiconductor substrate. The mixing and depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space. 1. A method for making an EUV-patternable film on a surface of a substrate , comprising:mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant so as to form a polymerized organometallic material; anddepositing the organometallic material onto the surface of the substrate to form the EUV-patternable film.2. The method of claim 1 , wherein the organometallic precursor has the formula{'br': None, 'MaRbLc,'}wherein: M is a metal with an atomic absorption cross section of 1×107 cm2/mol or higher; R is alkyl, such as CnH2n+1, wherein n≥3; L is a ligand, ion or other moiety which is reactive with the counter reactant; a≥1; b≥1; and c ≥1.3. The method of claim 2 , wherein M is selected from the group consisting of tin claim 2 , bismuth claim 2 , antimony claim 2 , and combinations thereof; R is selected from the group consisting i-propyl claim 2 , n-propyl claim 2 , t-butyl claim 2 , i-butyl claim 2 , n-butyl claim 2 , sec-butyl claim 2 , i-pentyl claim 2 , n-pentyl claim 2 , t-pentyl claim 2 , sec-pentyl and mixtures thereof; and L is selected from the group consisting of amines claim 2 , alkoxy claim 2 , carboxylates claim 2 , halogens claim 2 , and mixtures thereof.4. The method of claim 1 , wherein the organometallic precursor is t-butyl tris(dimethylamino) tin claim 1 , i-butyl tris(dimethylamino) tin claim ...

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Номер записи: 30
09-01-2020 дата публикации

SELECTIVE GROWTH OF SIO2 ON DIELECTRIC SURFACES IN THE PRESENCE OF COPPER

Номер: US20200013615A1
Автор: FOX Alexander R., Hausmann Dennis M., LAWLOR Colleen
Принадлежит:

Methods and apparatuses for selectively depositing silicon oxide on surfaces relative to a metal-containing surface such as copper are provided. Methods involve exposing a substrate having hydroxyl-terminated or dielectric surfaces and copper surfaces to a copper-blocking reagent such as an alkyl thiol to selectively adsorb to the copper surface, exposing the substrate to a silicon-containing precursor for depositing silicon oxide, exposing the substrate to a weak oxidant gas and igniting a plasma, or water vapor without plasma, to convert the adsorb silicon-containing precursor to form silicon oxide. Some methods also involve exposing the substrate to a reducing agent to reduce any oxidized copper from exposure to the weak oxidant gas. 1. A method of selectively depositing silicon oxide on a hydroxyl-terminated surface relative to copper on a substrate , the method comprising:providing the substrate comprising the hydroxyl-terminated surface and exposed copper metal surface;prior to depositing the silicon oxide, exposing the substrate to a copper-blocking reagent to selectively adsorb onto the exposed copper metal surface;exposing the substrate to a silicon-containing precursor to adsorb the silicon-containing precursor onto the hydroxyl-terminated surface;exposing the substrate to an oxidizing plasma generated in an environment comprising a weak oxidant to convert the adsorbed silicon-containing precursors to silicon oxide; andexposing the substrate to a reducing agent to reduce the exposed copper metal surface.2. The method of claim 1 , wherein the copper-blocking reagent comprises sulfur.3. The method of claim 1 , wherein the copper-blocking reagent is an alkyl thiol.4. The method of claim 3 , wherein the copper-blocking reagent is selected from the group consisting of ethane thiol and butane thiol.5. The method of claim 1 , wherein the copper-blocking reagent is an alkyl thiol having a chemical formula SH(CH)CHwhereby n is an integer between and including 2 and ...

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Номер записи: 31
09-01-2020 дата публикации

SUBSTRATE TREATMENT METHOD, SUBSTRATE TREATMENT SYSTEM AND DIRECTED SELF-ASSEMBLING MATERIAL

Номер: US20200013617A1
Автор: KOMATSU Hiroyuki, Nagai Tomoki, Osaki Hitoshi, SHIRATANI Motohiro, TAMADA Miki
Принадлежит: JSR Corporation

A substrate treatment method includes: overlaying a film on a surface of a substrate which includes a first region including a metal atom in a surface layer thereof, using a directed self-assembling material which contains a compound having no less than 6 carbon atoms and including at least one cyano group. After the overlaying, the film on a region other than the first region is removed. After the removing, a pattern principally containing a metal oxide is formed by an Atomic Layer Deposition process or a Chemical Vapor Deposition process on the region other than the first region, of the surface of the substrate. 1. A substrate treatment method comprising:overlaying a film on a surface of a substrate which comprises a first region comprising a metal atom in a surface layer thereof, using a directed self-assembling material which comprises a compound having no less than 6 carbon atoms and comprising at least one cyano group;after the overlaying, removing the film on a region other than the first region; andafter the removing, forming a pattern principally comprising a metal oxide by an Atomic Layer Deposition process or a Chemical Vapor Deposition process on the region other than the first region, of the surface of the substrate.3. The substrate treatment method according to claim 1 , further comprising after the forming of the pattern claim 1 , removing the compound that remains in the first region.4. The substrate treatment method according to claim 1 , wherein the overlaying comprises applying the directed self-assembling material on the surface of the substrate.5. A substrate treatment system comprising:a mechanism for overlaying a film on a surface of a substrate which comprises a first region comprising a metal atom in a surface layer thereof, using a directed self-assembling material which comprises a compound having no less than 6 carbon atoms and comprising at least one cyano group;a mechanism for removing the film on a region other than the first region, ...

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Номер записи: 32
21-01-2016 дата публикации

HARDMASK COMPOSITION AND METHOD OF FORMING PATTERNS USING THE HARDMASK COMPOSITION

Номер: US20160017174A1
Автор: KIM Hea-Jung, NAM Youn-Hee, SONG Hyun-Ji
Принадлежит:

A hardmask composition includes a polymer including a moiety represented by the following Chemical Formula 1 and a solvent.

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Номер записи: 33
21-01-2021 дата публикации

Structure body, sensor, and method for producing structure body

Номер: US20210017420A1
Автор: Akira NUKAZUKA, Hajime Shingai, Hitoshi Kuno, Kei Hayakawa
Принадлежит: Denso Corp

A structure body includes a base material and a siloxane based molecular membrane formed on the base material by use of an organic compound represented by Formula (1) or Formula (2): wherein any one of R1 to R5 is an amino group, others of R1 to R5 are each independently hydrogen or an alkyl group, R7 to R9 are each independently any one of hydroxy group, alkoxy group, alkyl group, and phenyl group on condition that one or more of R7 to R9 are each independently a hydroxy group or an alkoxy group, and R6 is an alkyl group.

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Номер записи: 34
03-02-2022 дата публикации

Method of manufacturing semiconductor structure and semiconductor structure

Номер: US20220037197A1
Автор: Che-Hsien LIAO, Ying-Cheng Chuang
Принадлежит: Nanya Technology Corp

A method of manufacturing a semiconductor structure includes: etching a substrate according to a hard mask to form a plurality of trenches in the substrate; performing a nitridation treatment on the trenches of the substrate; filling the trenches of the substrate with a flowable isolation material; and solidifying the flowable isolation material to form an isolation material. A semiconductor structure manufactured by the method is also provided.

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Номер записи: 35
03-02-2022 дата публикации

Conformal oxidation for gate all around nanosheet i/o device

Номер: US20220037529A1
Автор: Andy Lo, Benjamin Colombeau, Michael Stolfi, Myungsun Kim
Принадлежит: Applied Materials Inc

Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.

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Номер записи: 36
18-01-2018 дата публикации

SELF-LIMITING AND SATURATING CHEMICAL VAPOR DEPOSITION OF A SILICON BILAYER AND ALD

Номер: US20180019116A1
Автор: Chang Mei, EDMONDS Mary, KACHIAN Jessica S., KIM Hyunwoong, Kummel Andrew C., Park Sang Wook, Yoshida Naomi
Принадлежит:

Embodiments described herein provide a self-limiting and saturating Si—Obilayer process which does not require the use of a plasma or catalyst and that does not lead to undesirable substrate oxidation. Methods of the disclosure do not produce SiO, but instead produce a saturated Si—Ofilm with —OH termination to make substrate surfaces highly reactive towards metal ALD precursors to seed high nucleation and growth of gate oxide ALD materials. 1. A substrate processing method , comprising:heating a substrate in a reaction chamber to a temperature of less than 500° C.;exposing the substrate to a chlorosilane precursor utilizing a chemical vapor deposition process; andexposing the substrate to an anhydrous HOOH precursor utilizing the chemical vapor deposition process, wherein a chlorine terminated saturated silicon bilayer is deposited on the substrate.2. The method of claim 1 , wherein the substrate comprises one or more of indium gallium arsenide claim 1 , indium gallium antimonide claim 1 , indium gallium nitride claim 1 , silicon germanium claim 1 , and metallic materials.3. The method of claim 2 , wherein the reaction chamber is heated to a temperature of between 300° C. and 500° C.4. The method of claim 1 , wherein the chlorosilane precursor is selected from the group consisting of SiCl claim 1 , SiCl claim 1 , and SiCl.5. The method of claim 1 , further comprising:{'sub': 2', '6, 'exposing the substrate to an SiClprecursor utilizing an atomic layer deposition process; and'}{'sub': 2', '6, 'exposing the substrate to an anhydrous HOOH precursor utilizing the atomic layer deposition process, where in the atomic layer deposition process cyclically exposes the substrate to the SiClprecursor and the anhydrous HOOH precursor in an alternating manner.'}6. The method of claim 1 , further comprising:cleaning the substrate by a de-capping process or atomic H exposure prior to exposing the substrate to either of the chlorosilane precursor or the anhydrous HOOH precursor.7. ...

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Номер записи: 37
18-01-2018 дата публикации

INP-BASED TRANSISTOR FABRICATION

Номер: US20180019320A1
Автор: Adekore Bunmi, Cheng Zhiyuan, Fiorenza James, Wu Yanqing, Xuan Yi, Ye Peide
Принадлежит:

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP. 1. A method comprising:forming a mask layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant, the mask layer comprising a non-crystalline dielectric material;patterning the mask layer to form an opening in the mask layer, the opening exposing a portion of the substrate;forming a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, a topmost surface of the buffer layer being below a topmost surface of the mask layer, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening;forming a semiconductor layer over the buffer layer in the opening, the semiconductor layer comprising a third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant; andforming a gate stack over the semiconductor layer.2. The method of claim 1 , wherein the mask layer has a thickness between about 20 nm and about 50000 nm.3. The method of claim 1 , wherein a height of the opening is greater than or equal to a predetermined height claim 1 , and wherein the predetermined height is between one half of a width of the opening and two times the width of the opening.4. The method of claim 1 , wherein a ratio of a height of the opening to a width of the opening is ...

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Номер записи: 38
21-01-2021 дата публикации

METHOD FOR TUNING STRESS TRANSITIONS OF FILMS ON A SUBSTRATE

Номер: US20210020435A1
Автор: deVilliers Anton J., FULFORD Daniel, GRZESKOWIAK Jodi
Принадлежит: TOKYO ELECTRON LIMITED

The disclosure relates to a method for tuning stress transitions of films on a substrate. The method includes forming a stress-adjustment layer on the substrate, wherein the stress-adjustment layer includes first regions formed of a first material and second regions formed of a second material, wherein the first material includes a first internal stress and the second material includes a second internal stress, and wherein the first internal stress is different compared to the second internal stress; and forming transition regions between the first regions and the second regions, wherein the transition regions include an interface between the first material and the second material that has a predetermined slope that is greater than zero degrees and less than 90 degrees. 1. A method of adjusting stress on a substrate , the method comprising:depositing a first layer of a first material on the substrate;depositing a second layer of a second material on the first layer;changing a solubility of the second layer at one or more coordinate locations on the substrate, wherein the solubility of the second layer is changed in solubility from a top surface of the second layer down to a predetermined depth into the second layer at each of the one or more coordinate locations, and wherein changing the solubility of the second layer includes creating a transition region defining a predetermined slope of solubility change across the transition region; andremoving soluble portions of the second layer using a developer such that remaining portions of the second layer include the predetermined slope in the transition region from a first z-height of the second layer to a second z-height of the second layer, wherein the first z-height of the second layer is less than the second z-height of the second layer.2. The method of claim 1 , further comprising:executing an etch process that simultaneously etches the first material and the second material transferring the predetermined slope into ...

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Номер записи: 39
21-01-2021 дата публикации

METHOD FOR MITIGATING LATERIAL FILM GROWTH IN AREA SELECTIVE DEPOSITION

Номер: US20210020444A1
Автор: Tapily Kandabara N.
Принадлежит:

A substrate processing method for area selective deposition includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film. In one example, the first film contains a metal film, second film contains a metal-containing liner that surrounds the metal film, and the third film includes a dielectric film that surrounds the metal-containing liner. 1. A substrate processing method , comprising:providing a substrate containing a first film, a second film, and a third film;forming a first blocking layer on the first film;forming a second blocking layer on the second film, wherein the second blocking layer is different from the first blocking layer; andselectively forming a material film on the third film.2. The method of claim 1 , wherein the first film claim 1 , second film claim 1 , and the third film are selected from the group consisting of a metal film claim 1 , a metal-containing liner claim 1 , and a dielectric film.3. The method of claim 2 , wherein the metal-containing liner contains a metal compound or a second metal film that is different from the metal film.4. The method of claim 3 , wherein the metal compound includes TiN claim 3 , TaN claim 3 , MnO claim 3 , or AlO claim 3 , and the second metal film includes Co or Ru.5. The method of claim 2 , wherein the metal film includes Cu claim 2 , Al claim 2 , Ta claim 2 , Ti claim 2 , W claim 2 , Ru claim 2 , Co claim 2 , Ni claim 2 , Pt claim 2 , or Mo.6. The method of claim 2 , wherein the dielectric film includes SiO claim 2 , AlO claim 2 , HfO claim 2 , TiO claim 2 , ZrO claim 2 , SiN claim 2 , SiCN claim 2 , SiCOH claim 2 , or a combination or thereof7. The method of claim 1 , wherein the first blocking layer and the second blocking layer contain self- ...

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Номер записи: 40
21-01-2021 дата публикации

METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE

Номер: US20210020752A1
Автор: CHANG GUNG-PEI, CHANG Yao-Wen, Chu Ching-Sheng, Hsu Chern-Yow
Принадлежит:

The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A metal layer is formed. An adhesion-enhancing layer is formed over the metal layer by a silicide operation. A dielectric stack is formed over the adhesion-enhancing layer. A trench is formed in the dielectric stack by removing a portion of dielectric stack aligning with the metal layer. A barrier layer is formed conforming to the sidewall of the trench. A high-k dielectric layer is formed conforming to the barrier layer. A contact is formed in the trench and be connected to the metal layer. 1. A method for forming a semiconductor structure , comprising:forming a metal layer;forming an adhesion-enhancing layer over the metal layer by a silicide operation;forming a dielectric stack over the adhesion-enhancing layer;forming a trench in the dielectric stack by removing a portion of dielectric stack aligning with the metal layer;forming a barrier layer conforming to the sidewall of the trench;forming a high-k dielectric layer conforming to the barrier layer; andforming a contact in the trench and connecting to the metal layer.2. The method of claim 1 , further comprising:forming a sacrificial layer conforming to the high-k dielectric layer prior to forming the contact; andremoving the sacrificial layer after forming the contact.3. The method of claim 1 , wherein forming the adhesion-enhancing layer comprises applying silane over the metal layer.4. The method of claim 2 , wherein forming the dielectric stack comprises forming a silicon-rich silicon nitride interfacing with the adhesion-enhancing layer.5. The method of claim 4 , wherein the sacrificial layer is removed by hydrofluoric vapor.6. The method of claim 5 , further comprising:lining the barrier layer at a bottom of the trench; andremoving at least a portion of the high-k dielectric layer and the barrier layer from the bottom of the trench.7. The method of claim 6 , wherein forming the ...

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Номер записи: 41
28-01-2016 дата публикации

HYDROXYL GROUP TERMINATION FOR NUCLEATION OF A DIELECTRIC METALLIC OXIDE

Номер: US20160027640A1
Автор: Ando Takashi, Chudzik Michael P., DAI Min, Frank Martin M., Hilscher David F., JR. Joseph F., Krishnan Rishikesh, Linder Barry P., Ortolland Claude, Shepard
Принадлежит:

A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations. 1. A method of forming a semiconductor device comprising:providing a first device region having a first semiconductor material portion of a first semiconductor material;providing a second device region having a second semiconductor material portion of a second semiconductor material that is different from said first semiconductor material;forming a first semiconductor-containing dielectric material layer on said first semiconductor material portion and a second semiconductor-containing dielectric material layer on said second semiconductor material portion; andforming a metal oxide layer on said first semiconductor-containing dielectric material layer and said second semiconductor-containing dielectric material layer, wherein a portion of said metal oxide layer and a portion of each of said first semiconductor-containing dielectric material layer and said second semiconductor-containing dielectric material layer form a gate oxide material in each of said first and second device regions, wherein a difference in thickness of said gate oxide materials over said first device region and said second device region is less than 3 angstroms.2. The method of claim 1 , wherein said ...

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Номер записи: 42
02-02-2017 дата публикации

SILICON CARBIDE SEMICONDUCTOR DEVICES HAVING NITROGEN-DOPED INTERFACE

Номер: US20170032965A1
Автор: MacMillan Michael
Принадлежит:

Methods, systems, and devices are disclosed for implementing high power circuits and semiconductor devices. In one aspect, a method for fabricating a silicon carbide semiconductor device includes forming a thin epitaxial layer of a nitrogen doped SiC material on a SiC epitaxial layer formed on a SiC substrate, and thermally growing an oxide layer to form an insulator material on the nitrogen doped SiC epitaxial layer, in which the thermally grown oxide layer results in at least partially consuming the nitrogen doped SiC epitaxial layer in the oxide layer to produce an interface including nitrogen between the SiC epitaxial layer and the oxide layer. 1. A method for fabricating a silicon carbide (SiC) device , comprising:forming a thin epitaxial layer of a nitrogen doped SiC material on a SiC epitaxial layer formed on a SiC substrate; andthermally growing an oxide layer to form an insulator material on the nitrogen doped SiC epitaxial layer,wherein the thermally growing the oxide layer results in at least partially consuming the nitrogen doped SiC epitaxial layer in the oxide layer to produce an interface including nitrogen between the nitrogen doped SiC epitaxial layer and the oxide layer to create in the interface a spatial variation of a nitrogen concentration that decreases in distance from the nitrogen-doped SiC epitaxial layer below the interface to the oxide layer above the interface.2. The method as in claim 1 , wherein the insulator material includes silicon oxide.3. The method as in claim 1 , wherein the oxide layer is grown at a high temperature within a range 900° C. to 1200° C. in an oxidizing environment.4. The method as in claim 1 , wherein the nitrogen doped SiC epitaxial layer has a thickness less than 500 nm.5. The method as in claim 1 , wherein the nitrogen doped SiC material has a carrier concentration greater than 1×10cm.6. The method as in claim 1 , further comprising forming one or more transistor structures over the insulator material of the ...

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Номер записи: 43
04-02-2016 дата публикации

HANDLER WAFER REMOVAL BY USE OF SACRIFICIAL INERT LAYER

Номер: US20160035616A1
Автор: Cheng Kangguo, Faltermeier Johnathan E., Farooq Mukta G., Lin Wei, Skordas Spyridon, Winstel Kevin R.
Принадлежит:

The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer. 1. A method comprising:forming a sacrificial layer on a surface of the handler wafer, wherein the sacrificial layer comprises an inert material;forming a first dielectric layer on a surface of the sacrificial layer;forming a second dielectric layer on a surface of a semiconductor wafer;directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer, the bonding layer joining the semiconductor wafer and the handler wafer;andremoving the semiconductor wafer and the bonding layer from the handler wafer by degrading the sacrificial layer with infrared radiation, the infrared radiation passing through the handler wafer.2. The method of claim 1 , wherein the inert material comprises amorphous carbon.3. The method of claim 1 , wherein the handler wafer comprises a silicon substrate.4. The method of claim 1 , wherein the first dielectric layer comprises an oxide.5. The method of claim 1 , wherein the second dielectric layer comprises an oxide.6. The method of claim 1 , wherein the directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer comprises forming a dielectric bond.7. The method of claim 1 , wherein the ...

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Номер записи: 44
01-02-2018 дата публикации

ELECTRONIC APPARATUS AND MANUFACTURING METHOD OF THE SAME

Номер: US20180033617A1
Автор: HINATA Shoji, IMAZEKI Yoshikatsu
Принадлежит:

According to one embodiment, an electronic apparatus includes a first substrate including a first basement and a first conductive layer, a second substrate including a second basement, which is opposed to the first conductive layer and is separated from the first conductive layer, a second conductive layer, and a first hole penetrating the second basement, and a connecting material which electrically connects the first conductive layer and the second conductive layer via the first hole. 1. An electronic apparatus comprising:a first substrate comprising a first basement and a first conductive layer; a second basement, which is opposed to the first conductive layer and is separated from the first conductive layer,', 'a second conductive layer, and', 'a first hole penetrating the second basement; and, 'a second substrate comprisinga connecting material which electrically connects the first conductive layer and the second conductive layer via the first hole.2. The electronic apparatus according to claim 1 , wherein the first conductive layer includes a second hole opposed to the first hole.3. The electronic apparatus according to claim 2 , wherein:the first conductive layer includes a first upper surface, and a first inner surface facing the second hole; andthe connecting material is in contact with the first upper surface and the first inner surface.4. The electronic apparatus according to claim 2 , wherein the first basement includes a concavity opposed to the second hole.5. The electronic apparatus according to claim 4 , wherein the connecting material is in contact with the concavity.6. The electronic apparatus according to claim 1 , wherein the second conductive layer is located on the second basement on a side opposite to a side that is opposed to the first conductive layer.7. The electronic apparatus according to claim 2 , further comprising an organic insulating layer located between the first conductive layer and the second basement claim 2 ,wherein the organic ...

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Номер записи: 45
30-01-2020 дата публикации

Plasma processing method and plasma processing apparatus

Номер: US20200032395A1
Автор: Masanobu Honda, Michiko Nakaya, Shinya Ishikawa, Sho Kumakura, Toru Hisamatsu, Yoshihide Kihara
Принадлежит: Tokyo Electron Ltd

A plasma processing method executed by a plasma processing apparatus in the present disclosure includes a first step and a second step. In the first step, the plasma processing apparatus forms a first film on the side walls of an opening in the processing target, the first film having different thicknesses along a spacing between pairs of side walls facing each other. In the second step, the plasma processing apparatus forms a second film by performing a film forming cycle once or more times after the first step, the second film having different thicknesses along the spacing between the pairs of side walls facing each other.

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Номер записи: 46
31-01-2019 дата публикации

Interface Charge Reduction for SiGe Surface

Номер: US20190035923A1
Автор: Dechao Guo, Devendra Sadana, Gen Tsutsui, Hemanth Jagannathan, Joel P. de Souza, Marinus Hopstaken, Ruqiang Bao, Shogo Mochizuki, Stephen W. Bedell
Принадлежит: International Business Machines Corp

Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.

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Номер записи: 47
11-02-2016 дата публикации

COVERAGE OF HIGH ASPECT RATIO FEATURES USING SPIN-ON DIELECTRIC THROUGH A WETTED SURFACE WITHOUT A PRIOR DRYING STEP

Номер: US20160042945A1
Автор: Draeger Nerissa, Gottscho Richard, Hymes Diane, LIMARY Ratchana
Принадлежит:

A method includes depositing a film solution onto a patterned feature of a semiconductor substrate after wet cleaning the semiconductor substrate and without performing a drying step after the wet cleaning. The film solution includes a dielectric film precursor or a dielectric film precursor and at least one of a reactant, a solvent, a surfactant and a carrier fluid. The method includes baking at least one of solvent and unreacted solution out of a film formed by the film solution by heating the substrate to a baking temperature. The method includes curing the substrate. 1. A method comprising: without performing a drying step after wet cleaning the semiconductor substrate, depositing a film solution onto the patterned feature of the semiconductor substrate,', a dielectric film precursor; or', 'the dielectric film precursor and at least one of a reactant, a solvent, a surfactant and a carrier fluid; and, 'wherein the film solution includes, 'baking at least one of solvent and unreacted solution out of a film formed by the film solution by heating the substrate to a baking temperature., 'after wet cleaning a semiconductor substrate including a patterned feature2. The method of claim 1 , further comprising:prior to depositing the film solution and after wet cleaning, rinsing the patterned feature with a rinsing fluid.3. The method of claim 2 , wherein the rinsing fluid comprises at least one of water claim 2 , aqueous alcohol and a polar solvent.4. The method of claim 1 , further comprising curing the substrate after baking the film.5. The method of claim 4 , wherein the curing comprises at least one of heating claim 4 , thermal annealing claim 4 , ultraviolet (UV) curing claim 4 , plasma curing or chemically reactive curing.6. The method of claim 4 , wherein a curing temperature of the curing is greater than the baking temperature.7. The method of claim 1 , further comprising applying the film solution to the patterned feature using a spin-on approach.8. The method ...

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Номер записи: 48
11-02-2016 дата публикации

SEMICONDUCTOR COMPONENT AND METHOD

Номер: US20160043185A1
Автор: Liu Chun-Li
Принадлежит:

In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface and forming a passivation layer on the semiconductor material Portions of the passivation layer are removed and portions of the semiconductor material exposed by removing the portions of the passivation layer are also removed. A layer of dielectric material is formed on the passivation layer and the exposed portions of the semiconductor material and first and second cavities are formed in the layer of dielectric material. The first cavity exposes a first portion of the semiconductor material and has at least one step shaped sidewall and the second cavity exposes a second portion of the semiconductor material. A first electrode is formed in the first cavity and a second electrode is formed in the second cavity. 1. A method for manufacturing a semiconductor component , comprising:providing a semiconductor material having a surface;forming a passivation layer on the semiconductor material;removing first and second portions of the passivation layer and portions of the semiconductor material exposed by removing the first and second portions of the passivation layer;forming a layer of dielectric material on the passivation layer and the exposed portions of the semiconductor material;forming first and second cavities in the layer of dielectric material, the first cavity exposing a first portion of the semiconductor material and having at least one sidewall configured as a portion of a field plate, the second cavity exposing a second portion of the semiconductor material; andforming a first electrode in the first cavity and a second electrode in the second cavity.2. The method of claim 1 , wherein forming the first cavity comprises forming a first cavity portion having at least first and second sidewalls.3. The method of claim 2 , further including:forming the first sidewall of the first cavity portion to have a first step ...

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Номер записи: 49
09-02-2017 дата публикации

SELF-LIMITING AND SATURATING CHEMICAL VAPOR DEPOSITION OF A SILICON BILAYER AND ALD

Номер: US20170040159A1
Автор: Chang Mei, EDMONDS Mary, KACHIAN Jessica S., KIM Hyunwoong, Kummel Andrew C., Park Sang Wook, Yoshida Naomi
Принадлежит:

Embodiments described herein provide a self-limiting and saturating Si—Obilayer process which does not require the use of a plasma or catalyst and that does not lead to undesirable substrate oxidation. Methods of the disclosure do not produce SiO, but instead produce a saturated Si—Ofilm with —OH termination to make substrate surfaces highly reactive towards metal ALD precursors to seed high nucleation and growth of gate oxide ALD materials. 1. A substrate processing method , comprising:heating a substrate in a reaction chamber to a temperature of between about 300° C. and about 500° C.;exposing the substrate to a chlorosilane precursor utilizing a chemical vapor deposition process; andexposing the substrate to an anhydrous HOOH precursor utilizing the chemical vapor deposition process, wherein a chlorine terminated saturated silicon bilayer is deposited on the material substrate.2. The method of claim 1 , wherein the substrate comprises one or more of indium gallium arsenide claim 1 , indium gallium antimonide claim 1 , indium gallium nitride claim 1 , silicon germanium claim 1 , and metallic materials.3. The method of claim 2 , wherein the reaction chamber is heated to a temperature of about 350° C.4. The method of claim 1 , wherein the chlorosilane precursor is selected from the group consisting of SiCl claim 1 , SiCl claim 1 , and SiCl.5. The method of claim 1 , further comprising:{'sub': 2', '6, 'exposing the substrate to an SiClprecursor utilizing an atomic layer deposition process; and'}{'sub': 2', '6, 'exposing the substrate to an anhydrous HOOH precursor utilizing the atomic layer deposition process, where in the atomic layer deposition process cyclically exposes the substrate to SiCland anhydrous HOOH in an alternating manner.'}6. The method of claim 1 , further comprising:cleaning the substrate by a de-capping process or atomic H exposure prior to exposing the substrate to either of the chlorosilane precursor or the anhydrous HOOH precursor.7. The method ...

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Номер записи: 50
09-02-2017 дата публикации

METHOD FOR MANUFACTURING A BONDED SOI WAFER

Номер: US20170040210A1
Автор: MEGURO Kenji, NAKANO Masatake, WAKABAYASHI Taishi, Yagi Shinichiro, Yoshida Tomosuke
Принадлежит: SHIN-ETSU HANDOTAI CO., LTD.

A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick. 14-. (canceled)5. A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer , each composed of a silicon single crystal , via an insulator film , comprising the steps of:depositing a polycrystalline silicon layer on the bonding surface side of the base wafer,polishing a surface of the polycrystalline silicon layer,forming the insulator film on the bonding surface of the bond wafer,bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, andthinning the bonded bond wafer to form an SOI layer; wherein,as the base wafer, a silicon single crystal wafer having a resistivity of 100 Ω·cm or more is used,the step for depositing the polycrystalline silicon layer further comprises a stage for previously forming an oxide film on the surface of the base wafer on which the polycrystalline silicon layer is deposited, andthe polycrystalline silicon layer is deposited by two stages comprising a first growth performed at a first temperature of 1010° C. or less and a second growth performed at a ...

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Номер записи: 51
08-02-2018 дата публикации

Binary metal oxide based interlayer for high mobility channels

Номер: US20180040708A1
Автор: John Rozen, Vijay Narayanan, Yohei Ogawa
Принадлежит: International Business Machines Corp, Ulvac Inc

A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

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Номер записи: 52
08-02-2018 дата публикации

BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS

Номер: US20180040709A1
Автор: Narayanan Vijay, Ogawa Yohei, Rozen John
Принадлежит:

A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer. 1. A method of forming a binary alloy oxide based interlayer comprising:treating a semiconductor substrate with a wet chemical etchant to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer on the semiconductor substrate; andconverting the oxide containing interfacial layer to a binary alloy oxide using a plasma deposition sequence including alternating a metal gas precursor and a plasma selected from the group consisting of hydrogen, nitrogen or a combination thereof.2. The method of claim 1 , wherein the semiconductor substrate comprises a III-V semiconductor substrate.3. The method of claim 1 , wherein the wet chemical etchant comprises ammonium fluoride (NHF) claim 1 , hydrofluoric acid (HF) claim 1 , hydrochloric acid (HCl) claim 1 , ammonium hydroxide (NHOH) claim 1 , ammonium sulfide (NH)S and combinations thereof.4. The method of claim 1 , wherein the treating of the semiconductor substrate with the wet chemical etchant comprises a two stage treatment including a first surface treatment with ammonium hydroxide (NHOH) followed by a second surface treatment with ammonium sulfide (NH)S.5. The method of claim 2 , wherein the converting the oxide containing interfacial layer to a binary oxide based alloy using a plasma deposition sequence including alternating a metal gas precursor and the plasma employs an atomic layer deposition (ALD) apparatus.6. The method of ...

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Номер записи: 53
08-02-2018 дата публикации

BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS

Номер: US20180040710A1
Автор: Narayanan Vijay, Ogawa Yohei, Rozen John
Принадлежит:

A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer. 1. A semiconductor device comprising:a channel region of a semiconductor substrate composed of a type III-V semiconductor material;a gate structure including an interlayer that is present atop the channel region, the interlayer comprising at least one of oxygen and nitrogen, and a metal selected from the group consisting of aluminum, titanium, and a combination thereof, wherein the gate structure further includes a high-k dielectric layer directly atop the interlayer; andsource and drain regions on opposing sides of the channel region.2. The semiconductor device of claim 1 , wherein the interlayer comprises titanium aluminum oxynitride (TiAlON).3. The semiconductor device of claim 1 , wherein the interlayer has a thickness ranging from 10 Å to 20 Å.4. The semiconductor device of claim 1 , wherein the gate structure includes a metal nitride atop the high-k dielectric layer.5. The semiconductor device of claim 1 , wherein the channel region comprising FIN structures.6. The semiconductor device of claim 1 , wherein the channel region comprises nanowires.7. The semiconductor device of claim 1 , wherein the channel region is orientated for a vertical field effect transistor.8. The semiconductor device of claim 1 , wherein the channel region comprises nanosheets.9. A semiconductor device comprising:a channel region of a semiconductor substrate composed of a type III-V semiconductor material;a gate structure ...

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Номер записи: 54
07-02-2019 дата публикации

Method and apparatus for forming silicon oxide film on tungsten film

Номер: US20190043712A1
Автор: Koji Sasaki, Kyungseok KO, Toshiyuki Ikeuchi
Принадлежит: Tokyo Electron Ltd

A method for forming a silicon oxide film on a tungsten film includes performing a first process of arranging an object to be processed in a processing container kept under a reduced pressure, the object including a tungsten film and a natural oxide film being formed on a surface of the tungsten film, performing a second process of forming a silicon seed layer by adsorbing a silicon-containing gas to the tungsten film, subsequently performing a third process of annealing the object and forming the silicon oxide film by a reaction of the natural oxide film and the silicon seed layer and subsequently performing a fourth process of forming an ALD silicon oxide film by ALD using a silicon-containing gas and an oxygen active species.

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Номер записи: 55
07-02-2019 дата публикации

MANUFACTURING SYSTEM AND METHOD FOR FORMING A CLEAN INTERFACE BETWEEN A FUNCTIONAL LAYER AND A TWO-DIMENSIONAL LAYEYED SEMICONDUCTOR

Номер: US20190043720A1
Автор: LIAO CHIU-CHUAN, LIN Yi-Ping, Yeh Chao-Hui
Принадлежит:

A manufacturing system and a method for forming a clean interface between a functional layer and a 2D layered semiconductor are provided herein. In the steps of the method, the substrate equipped with the 2D layered semiconductor is exposed to a reaction gas, and a stimulus is applied to the reaction gas to generate active particles having higher selectivity toward contaminants on the exposed surface of the 2D layered semiconductor so that the contaminants can be decomposed and removed. Additionally, the contaminants can be removed without damage to the 2D layered semiconductor. A functional layer is in-situ deposited to be in contact with the 2D layered semiconductor. Without the contaminants, a clean interface between the functional layer and the 2D layered semiconductor can be obtained and the 2D layered semiconductor can exhibit better electrical properties. 1. A method for forming a contact between a functional layer and a 2D layered semiconductor comprising:providing a substrate having the 2D layered semiconductor, wherein the 2D layered semiconductor is a metal based chalcogenide film;forming a photoresist layer on the 2D layered semiconductor;patterning the photoresist layer to form at least one contact opening;exposing the substrate equipped with the 2D layered semiconductor and the patterned photoresist layer to a reaction gas;inducing a chemical reaction on the reaction gas by periodically providing a stimulus to generate active particles having higher selectivity toward contaminants on the exposed surface of the 2D layered semiconductor so that the contaminants are removed; andin-situ forming a functional layer within the at least one contact opening to be in contact with the 2D layered semiconductor.2. (canceled)3. The method according to claim 1 , wherein the photoresist residues are formed separately in the at least one contact opening.4. The method according to claim 1 , wherein the stimulus is UV radiation and the reaction gas is oxygen gas or ...

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Номер записи: 56
06-02-2020 дата публикации

PROTECTIVE MEMBER FORMING APPARATUS

Номер: US20200043754A1
Автор: NAMIOKA Shinichi
Принадлежит:

A holding table for holding a wafer includes plural pins, and a wafer holding surface includes the tips of the plural pins. Therefore, small dust enters between the pins and thus is less readily left between the wafer holding surface and the wafer. Therefore, when the wafer is sucked and held, a gap is less readily made between the wafer holding surface and the wafer. Thus, the occurrence of the situation in which the wafer is held in a waving state is suppressed. For this reason, when a liquid resin is pushed to spread over the lower surface of the wafer, an air bubble enters less readily between the liquid resin and the wafer. This can suppress entry of the air bubble in a protective member obtained by curing the liquid resin. 1. A protective member forming apparatus comprising:a holding table having a workpiece holding surface that sucks and holds an upper surface of a workpiece;a stage that is disposed opposed to the workpiece holding surface and holds a lower surface of a film;resin supply means that supplies a liquid resin onto an upper surface of the film held by the stage;expanding means that pushes and spreads the liquid resin on the upper surface of the film by a lower surface of the workpiece held by the workpiece holding surface by causing the holding table to move in such a direction as to come closer to the stage; andcuring means that cures the liquid resin pushed to spread and forms a protective member, wherein a base with a flat plate shape,', 'a plurality of pins disposed upright in a downward direction on a lower surface of the base,', 'an annular wall that surrounds the plurality of pins and has a lower surface with the same height as tips of the pins, and', 'a suction path that penetrates the base and communicates with a suction source inside the annular wall., 'the holding table includes'}2. The protective member forming apparatus according to claim 1 , wherein a ring frame,', 'an adhesive tape that closes an opening of the ring frame and has a ...

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Номер записи: 57
18-02-2016 дата публикации

Method of manufacturing display apparatus

Номер: US20160049457A1
Автор: Tae-Gon Kim
Принадлежит: Samsung Display Co Ltd

A display apparatus includes a plurality of pixels, a signal transmission line, a pad and a buffer. The pixels display an image. The signal transmission line is electrically connected to at least one of the pixels to transmit a signal. The pad is electrically connected to the signal transmission line. The pad has greater width than the signal transmission line. The buffer is disposed between the signal transmission line and the pad. A first end of the buffer adjacent to the pad is wider than a second end of the buffer adjacent to the signal transmission line.

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Номер записи: 58
18-02-2016 дата публикации

PROCESS FOR FABRICATING SILICON NANOSTRUCTURES

Номер: US20160049471A1
Автор: BLACK Marcie R., Buchine Brent A., Modawar Faris
Принадлежит:

A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent. 1. A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures , the process comprising:depositing metal on top of the substrate; andcontacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.2. The process of claim 1 , further comprising selecting a method of metal deposition and selecting the oxidizing agent such that the process results in formation of an array of nanostructures oriented substantially vertically relative to the top of the substrate.3. The process of claim 2 , further comprising selecting the method of metal deposition and selecting the oxidizing agent such that the process results in formation of nanostructured arrays in which an average diameter of the nanostructures is less than about 125 nm.4. The process of claim 1 , further comprising selecting a method of metal deposition and selecting the oxidizing agent such that the process results in formation of nanostructures oriented substantially and approximately perpendicular to the top of the substrate.5. The process of claim 1 , wherein depositing the metal comprises depositing the metal as a continuous film.6. The process of claim 1 , wherein the oxidizing agent is oxygen gas and the process further comprises bubbling the oxygen gas through the etchant aqueous solution.7. The process of claim 1 , wherein the metal deposited on top of the substrate is silver.8. The process of claim 7 , wherein the silver is deposited by sputtering.9. The process of claim 7 , wherein the silver is deposited as a continuous film.10. The process of claim 1 , further comprising depositing nanoparticles of ...

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Номер записи: 59
14-02-2019 дата публикации

SOLUTION DEPOSITION METHOD FOR FORMING METAL OXIDE OR METAL HYDROXIDE LAYER

Номер: US20190048488A1
Автор: "OHara Evan C.", ESTRADA Daniel, Richardson Jacob J.
Принадлежит:

A solution deposition method includes: applying a liquid precursor solution to a substrate, the precursor solution including an oxide of a first metal, a hydroxide of the first metal, or a combination thereof, dissolved in an aqueous ammonia solution; evaporating the precursor solution to directly form a solid seed layer on the substrate, the seed layer including an oxide of the first metal, a hydroxide of the first metal, or a combination thereof, the seed layer being substantially free of organic compounds; and growing a bulk layer on the substrate, using the seed layer as a growth site or a nucleation site. 1. An optoelectronic device , comprising:a substrate comprising epitaxial layers of a group III-Nitride semiconductor;an epitaxial seed layer formed on the substrate, the seed layer comprising an oxide of a first metal, a hydroxide of the first metal, or a combination thereof, and the seed layer being substantially free of organic compounds;an epitaxial bulk layer formed on the seed layer.2. The optoelectronic device of claim 1 , wherein the seed layer has a thickness of from about 2 nm to about 20 nm.3. The optoelectronic device of claim 1 , wherein the seed layer covers only a selected portion of the surface of the substrate claim 1 , and the bulk layer is disposed only on the selected portion.4. The optoelectronic device of claim 1 , wherein the seed layer is a ZnO seed layer and includes at least one additional element selected from the group of Li claim 1 , Na claim 1 , Be claim 1 , Mg claim 1 , Ti claim 1 , Zr claim 1 , Hf claim 1 , Cr claim 1 , Mo claim 1 , W claim 1 , Mn claim 1 , Fe claim 1 , Co claim 1 , Ni claim 1 , Cu claim 1 , Cd claim 1 , Al claim 1 , Ga claim 1 , In claim 1 , Si claim 1 , Ge claim 1 , Sn claim 1 , P claim 1 , As claim 1 , S claim 1 , Se claim 1 , and F.5. The optoelectronic device of claim 4 , wherein the bulk layer comprises ZnO.6. The optoelectronic device of claim 1 , wherein the bulk layer comprises an oxide of second metal ...

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Номер записи: 60
13-02-2020 дата публикации

ADHESIVE FILM AND METHOD OF MANUFACTURING ELECTRONIC APPARATUS

Номер: US20200048501A1
Автор: IGARASHI Kouji, KINOSHITA Jin, KURIHARA Hiroyoshi
Принадлежит: Mitsui Chemicals Tohcello, Inc.

An adhesive film used when sealing an electronic component to temporarily fix the electronic component, the adhesive film including a base material layer, an adhesive resin layer which is provided on a first surface side of the base material layer and which is for temporarily fixing the electronic component, and an adhesive resin layer which is provided on a second surface side of the base material layer and of which the adhesive strength decreases according to an external stimulus, in which the adhesive resin layer includes a polyvalent carboxylic acid ester-based plasticizer and an adhesive resin, and a content of the polyvalent carboxylic acid ester-based plasticizer in the adhesive resin layer is more than or equal to 0.7 parts by mass and less than or equal to 50 parts by mass with respect to 100 parts by mass of the adhesive resin included in the adhesive resin layer. 1. An adhesive film used when sealing an electronic component with a sealing material in a step of manufacturing an electronic apparatus to temporarily fix the electronic component , the adhesive film comprising:a base material layer;an adhesive resin layer (A) which is provided on a first surface side of the base material layer and which is for temporarily fixing the electronic component; andan adhesive resin layer (B) which is provided on a second surface side of the base material layer and of which adhesive strength decreases according to an external stimulus,wherein the adhesive resin layer (A) includes a polyvalent carboxylic acid ester-based plasticizer (X) and an adhesive resin (Y), anda content of the polyvalent carboxylic acid ester-based plasticizer (X) in the adhesive resin layer (A) is more than or equal to 0.7 parts by mass and less than or equal to 50 parts by mass with respect to 100 parts by mass of the adhesive resin (Y) included in the adhesive resin layer (A).2. The adhesive film according to claim 1 ,wherein the polyvalent carboxylic acid ester-based plasticizer (X) includes ...

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Номер записи: 61
03-03-2022 дата публикации

DIFFUSION BARRIERS FOR GERMANIUM

Номер: US20220068640A1
Автор: Ingle Nitin K., KOSHIZAWA Takehito, Mallick Abhijit Basu, Qi Bo, Singha Roy Susmit, Wang Huiyuan
Принадлежит: Applied Materials, Inc.

Examples of the present technology include semiconductor processing methods to form diffusion barriers for germanium in a semiconductor structure. The methods may include forming a semiconductor layer stack from pairs of Si-and-SiGe layers. The Si-and-SiGe layer pairs may be formed by forming a silicon layer, and then forming the germanium barrier layer of the silicon layer. In some embodiments, the germanium-barrier layer may be less than or about 20 Å. A silicon-germanium layer may be formed on the germanium-barrier layer to complete the formation of the Si-and-SiGe layer pair. In some embodiments, the silicon layer may be an amorphous silicon layer, and the SiGe layer may be characterized by greater than or about 5 atom % germanium. Examples of the present technology also include semiconductor structures that include a silicon-germanium layer, a germanium-barrier layer, and a silicon layer.

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Номер записи: 62
25-02-2016 дата публикации

METHOD TO TUNE TIOX STOICHIOMETRY USING ATOMIC LAYER DEPOSITED TI FILM TO MINIMIZE CONTACT RESISTANCE FOR TIOX/TI BASED MIS CONTACT SCHEME FOR CMOS

Номер: US20160056037A1
Автор: Arghavani Reza, Danek Michal, Gopinath Sanjay, Karim Ishtak, Thombare Shruti Vivek
Принадлежит:

Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate. 1. A method of forming titanium oxide on a semiconductor substrate in a chamber , the method comprising: (i) exposing the substrate to titanium tetraiodide,', '(ii) purging the chamber,', '(iii) exposing the substrate to an ignited plasma, and', '(iv) purging the chamber, and', '(v) repeating (i) through (iv) until the desired thickness of titanium is deposited; and, '(a) depositing titanium on the substrate, wherein depositing titanium comprises(b) treating the substrate to form sub-stoichiometric titanium oxide.2. The method of claim 1 , wherein the sub-stoichiometric titanium oxide comprises titanium oxide having the chemical formula TiO claim 1 , where x<2.3. The method of claim 1 , wherein the titanium is deposited at a temperature less than about 400° C.4. The method of claim 1 , further comprising prior to depositing the titanium claim 1 , depositing a layer of titanium oxide on the substrate.5. The method of claim 4 , wherein the layer of titanium oxide is formed by exposing the substrate to a titanium-containing precursor.6. The method of claim 1 , wherein treating the substrate comprises exposing the substrate to the titanium-containing precursor and an oxidant.7. The method of claim 6 , wherein the oxidant is selected from the group consisting of oxygen claim 6 , nitrous oxide claim 6 , water vapor claim 6 , hydrogen peroxide claim ...

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Номер записи: 63
14-02-2019 дата публикации

Multiple barrier layer encapsulation stack

Номер: US20190051570A1
Автор: Avanti M. JAIN, Jean-Christophe Giron
Принадлежит: Sage Electrochromics Inc

A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying multiple barrier layers to the apparatus and preceding each layer application with a separate cleaning of the presently-exposed apparatus surface, resulting in an apparatus which includes an encapsulation stack, where the encapsulation stack includes a multi-layer stack of barrier layers. Each separate cleaning removes particles from the presently-exposed apparatus surface, exposing gaps in the barrier layer formed by the particles, and the subsequently-applied barrier layer at least partially fills the gaps, so that a permeation pathway through the encapsulation stack via gap spaces is restricted. The quantity of barrier layers applied to form the stack can be based on a determined probability that a stack of the particular quantity of barrier layers is independent of at least a certain quantity of continuous permeation pathways through the stack.

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Номер записи: 64
14-02-2019 дата публикации

Coating liquid for forming n-type oxide semiconductor film, method for producing n-type oxide semiconductor film, and method for producing field-effect transistor

Номер: US20190051752A1
Автор: Minehide KUSAYANAGI, Naoyuki Ueda, Ryoichi SAOTOME, Sadanori ARAE, Shinji Matsumoto, Yuji Sone, Yuki Nakamura, Yukiko Abe
Принадлежит: Ricoh Co Ltd

A coating liquid for forming an n-type oxide semiconductor film, the coating liquid including: a Group A element, which is at least one selected from the group consisting of Sc, Y, Ln, B, Al, and Ga; a Group B element, which is at least one of In and Tl; a Group C element, which is at least one selected from the group consisting of Group 4 elements, Group 5 elements, Group 6 elements, Group 7 elements, Group 8 elements, Group 9 elements, Group 10 elements, Group 14 elements, Group 15 elements, and Group 16 elements; and a solvent.

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Номер записи: 65
25-02-2021 дата публикации

TREATMENTS TO ENHANCE MATERIAL STRUCTURES

Номер: US20210057215A1
Автор: HUNG Steven C. H.
Принадлежит:

A method of forming a semiconductor structure includes pre-cleaning a surface of a substrate, forming an interfacial layer on the pre-cleaned surface of the substrate, depositing a high-κ dielectric layer on the interfacial layer, performing a plasma nitridation process to insert nitrogen atoms in the deposited high-κ dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-κ dielectric layer. 1. A method of forming a semiconductor structure , the method comprising: pre-cleaning a surface of a substrate;', 'forming an interfacial layer on the pre-cleaned surface of the substrate;', 'depositing a high-κ dielectric layer on the interfacial layer;', 'performing a plasma nitridation process to insert nitrogen atoms in the deposited high-κ dielectric layer; and', 'performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-κ dielectric layer., 'forming a semiconductor structure, comprising2. The method of claim 1 , wherein the forming of the semiconductor structure is performed in a processing system without breaking vacuum.3. The method of claim 1 , wherein{'sub': '2', 'the interfacial layer comprises silicon oxide (SiO), and'}{'sub': '2', 'the forming of the interfacial layer comprises thermally oxidizing the substrate utilizing nitrous oxide (NO) gas.'}4. The method of claim 1 , wherein the high-κ dielectric layer comprises hafnium oxide (HfO).5. The method of claim 1 , wherein the plasma nitridation process comprises exposing the deposited high-κ dielectric layer to nitrogen plasma using a mixture of nitrogen (N) and ammonia (NH) gas.6. The method of claim 1 , wherein the post-nitridation anneal process comprises spike annealing the deposited high-κ dielectric layer in a nitrogen (N) and argon (Ar) ambient at a temperature of between of between 700° C. and 850° C.7. The method of claim 1 , further comprising:performing a post-deposition anneal process, prior ...

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Номер записи: 66
23-02-2017 дата публикации

SELECTIVE ATOMIC LAYER DEPOSITION PROCESS UTILIZING PATTERNED SELF ASSEMBLED MONOLAYERS FOR 3D STRUCTURE SEMICONDUCTOR APPLICATIONS

Номер: US20170053797A1
Автор: FAN Yin, Godet Ludovic, Nemani Srinivas D., YIEH Ellie Y.
Принадлежит:

Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer. 1. A method of forming a structure with desired materials on a substrate comprising:forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer; andperforming an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.2. The method of claim 1 , wherein the patterned self-assembled monolayer is formed by the following steps:depositing the self-assembled monolayer on the structure; andperforming a directional plasma process on the self-assembled monolayer to form the patterned the self-assembled monolayer with the treated layer patterning the self-assembled monolayer.3. The method of claim 2 , wherein the directional plasma process further comprises:doping ions predominantly into the self-assembled monolayer disposed on a first sidewall of the structure to form the treated layer.4. The method of claim 3 , wherein doping ions further comprises:leaving the self-assembled monolayer formed on a second sidewall of the structure without ions doped thereto.5. The method of claim 3 , wherein doping ions further ...

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Номер записи: 67
23-02-2017 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20170053990A1
Автор: Naoya Okamoto, Shirou Ozaki
Принадлежит: Fujitsu Ltd

A semiconductor device includes: a semiconductor layer; a first insulating film which covers a surface of the semiconductor layer; a first adhering film which is formed on a surface of the first insulating film and contains a carbonyl group; and a second insulating film which covers a surface of the first adhering film and has a lower dielectric constant than the first insulating film.

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Номер записи: 68
01-03-2018 дата публикации

Substrate processing method

Номер: US20180061633A1
Автор: Rei Takeaki, Sadamu Fujii, Taiki HINODE
Принадлежит: Screen Holdings Co Ltd

A substrate processing method includes a facing-disposing step of disposing a facing member such that the facing member faces an upper surface of the horizontally held substrate, a space forming step of forming a space where movement of the atmosphere in from and out to an outside is restricted by the horizontally held substrate, the facing member, and a guard that surrounds the horizontally held substrate and the facing member in plan view, an inert gas supplying step of supplying an inert gas to the space, an interval adjusting step of adjusting an interval between the upper surface of the substrate and the facing member by relatively raising/lowering the facing member with respect to the horizontally held substrate while maintaining the space, and a processing liquid supplying step of supplying a processing liquid to the upper surface of the horizontally held substrate after the interval adjusting step.

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Номер записи: 69
02-03-2017 дата публикации

METHODS AND APPARATUS FOR IN-SITU CLEANING OF COPPER SURFACES AND DEPOSITION AND REMOVAL OF SELF-ASSEMBLED MONOLAYERS

Номер: US20170062210A1
Автор: Arnepalli Ranga Rao, GORADIA Prerna, Visser Robert Jan
Принадлежит:

A method of processing includes: providing a substrate having a contaminant material disposed on the copper surface to a substrate support within a hot wire chemical vapor deposition (HWCVD) chamber; providing hydrogen (H) gas to the HWCVD chamber; heating one or more filaments disposed in the HWCVD chamber to a temperature sufficient to dissociate the hydrogen (H) gas; exposing the substrate to the dissociated hydrogen (H) gas to remove at least some of the contaminant material from the copper surface; cooling the one or more filaments to room temperature; exposing the substrate in the HWCVD chamber to one or more chemical precursors to deposit a self-assembled monolayer atop the copper surface; and depositing a second layer atop the substrate. 1. A method of processing a substrate having an exposed copper surface , comprising:(a) providing a substrate having a contaminant material disposed on the copper surface to a substrate support within a hot wire chemical vapor deposition (HWCVD) chamber;{'sub': '2', '(b) providing hydrogen (H) gas to the HWCVD chamber;'}{'sub': '2', '(c) heating one or more filaments disposed in the HWCVD chamber to a temperature sufficient to dissociate the hydrogen (H) gas;'}{'sub': '2', '(d) exposing the substrate to the dissociated hydrogen (H) gas to remove at least some of the contaminant material from the copper surface;'}(e) cooling the one or more filaments to room temperature;(f) exposing the substrate in the HWCVD chamber to one or more chemical precursors to deposit a self-assembled monolayer atop the copper surface; and(g) depositing a second layer atop the substrate.2. The method of claim 1 , wherein depositing the second layer further comprises:after depositing the self-assembled monolayer, selectively depositing a dielectric layer atop an exposed silicon-containing surface of the substrate in the HWCVD chamber;{'sub': '2', 'providing hydrogen (H) gas to the HWCVD chamber;'}{'sub': '2', 'heating the one or more filaments ...

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Номер записи: 70
17-03-2022 дата публикации

NOZZLE STANDBY DEVICE, LIQUID PROCESSING APPARATUS AND OPERATION METHOD OF LIQUID PROCESSING APPARATUS

Номер: US20220084844A1
Автор: Inada Hiroichi, KAWAKAMI Kohei, SHIMMURA Satoshi, TAKAYANAGI Koji
Принадлежит:

A nozzle standby device configured to allow a nozzle to stand by therein includes a nozzle accommodation unit, having an inner circumferential surface formed to surround a leading end portion of the nozzle, provided with a drain opening facing a discharge opening of the nozzle; and a solvent discharge opening opened within the nozzle accommodation unit. The nozzle accommodation unit has a diameter reducing portion having a first and a second inner circumferential surfaces having different angles with respect to a center line of the nozzle accommodation unit such that an inner diameter of the diameter reducing portion becomes smaller toward the drain opening. An intersection point of two straight lines extending along two opposite portions of the first inner circumferential surface is located above the discharge opening of the nozzle when the leading end portion of the nozzle is placed in the diameter reducing portion. 1. A nozzle standby device configured to allow a nozzle configured to discharge a processing liquid , which is to be solidified by being dried , to stand by therein , the nozzle standby device comprising:a nozzle accommodation unit, having an inner circumferential surface formed to surround a leading end portion of the nozzle, provided with a drain opening facing a discharge opening of the nozzle; anda solvent discharge opening opened within the nozzle accommodation unit, and formed such that a discharged solvent is guided along the inner circumferential surface of the nozzle accommodation unit to be drained from the drain opening,wherein the nozzle accommodation unit has, in a region above the drain opening where the solvent discharged from the solvent discharge opening falls down as a swirling flow, a diameter reducing portion having a first inner circumferential surface and a second inner circumferential surface as the inner circumferential surface such that an inner diameter of the diameter reducing portion becomes smaller toward the drain opening, ...

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Номер записи: 71
10-03-2016 дата публикации

ENHANCING ELECTRICAL PROPERTY AND UV COMPATIBILITY OF ULTRATHIN BLOK BARRIER FILM

Номер: US20160071724A1
Автор: BA Xiaolan, Demos Alexandros T., JIN Yu, Padhi Deenesh, Shek Mei-yee, Xia Li-Qun, YE Weifeng
Принадлежит:

Embodiments described herein generally relate to the formation of a UV compatible barrier stack. Methods described herein can include delivering a process gas to a substrate positioned in a process chamber. The process gas can be activated to form an activated process gas, the activated process gas forming a barrier layer on a surface of the substrate, the barrier layer comprising silicon, carbon and nitrogen. The activated process gas can then be purged from the process chamber. An activated nitrogen-containing gas can be delivered to the barrier layer, the activated nitrogen-containing gas having a N:NHratio of greater than about 1:1. The activated nitrogen-containing gas can then be purged from the process chamber. The above elements can be performed one or more times to deposit the barrier stack. 1. A method of depositing a barrier layer , comprising:positioning a substrate in a process chamber;activating a process gas to form a barrier layer on a surface of the substrate, the barrier layer comprising silicon, carbon and nitrogen;purging the activated process gas from the process chamber;{'sub': 2', '3, 'delivering an activated nitrogen-containing gas to the barrier layer, the activated nitrogen-containing gas having a N:NHratio of greater than about 1:1; and'}purging the activated nitrogen-containing gas from the process chamber.2. The method of claim 1 , wherein the N:NHratio of the activated nitrogen-containing gas is greater than about 10:1.3. The method of claim 1 , wherein the N:NHratio of the activated nitrogen-containing gas is about 100:1.4. The method of claim 1 , wherein the Nconcentration of the activated nitrogen-containing gas is approximately equal to the Ar concentration of the activated nitrogen-containing gas.5. The method of claim 1 , wherein the process gas comprises bis(diethylamino) silane (BDEAS) claim 1 , hexamethylcyclotrisilazane (HMCTZ) claim 1 , trimethylsilane (TMS) or combinations thereof.6. The method of claim 1 , wherein the ...

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Номер записи: 72
28-02-2019 дата публикации

INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION THEREOF

Номер: US20190067197A1
Автор: Chen Yen-Ming, Chui Chi On, Lee Kai-Hsuan, Yeong Sai-Hooi, YU Chia-Ta
Принадлежит:

Methods and devices for forming a conductive line disposed over a substrate. A first dielectric layer is disposed over the substrate and coplanar with the conductive line. A second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer. A via extends through the second dielectric layer and is coupled to the conductive line. The second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition. In some embodiments, the second dielectric layer is selectively deposited on the conductive line. 1. A device , comprising:a conductive line disposed over a substrate;a first dielectric layer disposed over the substrate and coplanar with the conductive line;a second dielectric layer disposed over the conductive line and a third dielectric layer disposed over the first dielectric layer, wherein the second dielectric layer and the third dielectric layer are coplanar and the second and third dielectric layers have a different composition; anda via extending through the second dielectric layer and coupled to the conductive line.2. The device of claim 1 , wherein a first sidewall of the via interfaces the second dielectric layer and a second sidewall of the via interfaces the third dielectric layer.3. The device of claim 2 , wherein a bottom surface of the via interfaces the conductive line and a top surface of the via interfaces another conductive line.4. The device of claim 1 , wherein the second dielectric layer is a nitride and the third dielectric layer is an oxide.5. The device of claim 1 , wherein the first dielectric layer and the third dielectric layer have a same composition.6. The device of claim 1 , wherein the second dielectric layer is silicon nitride.7. A device comprising:a conductive feature in a first dielectric layer disposed over a substrate;a second dielectric layer interfacing the conductive feature and a third dielectric ...

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Номер записи: 73
11-03-2021 дата публикации

Method of selective deposition for forming fully self-aligned vias

Номер: US20210074584A1
Автор: Kandabara Tapily
Принадлежит: Tokyo Electron Ltd

Methods are provided for selective film deposition. One method includes providing a substrate containing a dielectric material and a metal layer, the metal layer having an oxidized metal layer thereon, coating the substrate with a metal-containing catalyst layer, treating the substrate with an alcohol solution that removes the oxidized metal layer from the metal layer along with the metal-containing catalyst layer on the oxidized metal layer, and exposing the substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO 2 film on the metal-containing catalyst layer on the dielectric material.

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Номер записи: 74
11-03-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20210074804A1
Автор: Huang Tse-Yao
Принадлежит:

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a conductive feature comprising tungsten positioned above the substrate, a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature, and a plurality of capacitor structures positioned above the substrate. 1. A semiconductor device , comprising:a substrate;a conductive feature comprising tungsten positioned above the substrate;a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature;a plurality of capacitor structures positioned above the substrate; anda plurality of word lines positioned in the substrate and a doped region positioned between an adjacent pair of the plurality of word lines, wherein the conductive feature is positioned on the doped region.2. The semiconductor device of claim 1 , wherein the conductive feature is positioned below the plurality of capacitor structures.3. The semiconductor device of claim 1 , wherein the conductive feature is positioned above the plurality of capacitor structures.4. (canceled)5. The semiconductor device of claim 1 , further comprising a plurality of isolation structures positioned in the substrate claim 1 , wherein the plurality of isolation structures are separated from each other and define a plurality of active regions of the substrate.6. The semiconductor device of claim 5 , further comprising a doped region claim 5 , wherein each of the plurality of active regions intersects two word lines claim 5 , the doped region is positioned between one of the two word lines and one of the plurality of isolation structures claim 5 , and the conductive feature is positioned on the doped region.7. The semiconductor device of claim 6 , wherein the two word lines extend along a first direction and the plurality of active regions extend along a direction that is slanted with respect to the first ...

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Номер записи: 75
11-03-2021 дата публикации

EMBEDDED SONOS WITH TRIPLE GATE OXIDE AND MANUFACTURING METHOD OF THE SAME

Номер: US20210074821A1
Автор: Keshavarzi Ali, Kouznetsov Igor, Prabhakar Venkatraman, Ramkumar Krishnaswamy
Принадлежит:

A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness. 1forming a dielectric stack, including a cap layer, overlying first and second regions of a substrate;patterning the dielectric stack to form a non-volatile (NV) gate stack of a non-volatile memory (NVM) transistor in the first region while concurrently removing the dielectric stack in the second region;performing a first oxidation process to form a first gate oxide layer overlying the second region;removing the first gate oxide layer from second and third areas of the second region, but leaving the first gate oxide layer in a first area of the second region;performing a second oxidation process to form a second gate oxide layer in the second region, to concurrently consume at least a portion of the cap layer to form a blocking oxide of the NVM transistor in the first region, and to increase a thickness of the first gate oxide layer in the first area; andremoving the second gate oxide layer in the third area of the second region.. A method, comprising: The present application is a continuation application of U.S. Non-Provisional application Ser. No. 15/683,274, filed on Aug. 22, 2017, which claims the priority and benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 62/519,757, filed on Jun. 14, 2017, all of which are incorporated by reference herein in their entirety.The present disclosure relates generally ...

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Номер записи: 76
19-03-2015 дата публикации

CHEMICAL DIELECTRIC FORMATION FOR SEMICONDUCTOR DEVICE FABRICATION

Номер: US20150079775A1
Автор: WU SHAO-JYUN
Принадлежит: Taiwan Semiconductor Manufacturing Company Limited

Systems and methods are provided for fabricating semiconductor devices. For example, a substrate is provided. A polymer layer is formed on the substrate. An oxygen-based plasma is applied to remove the polymer layer. An oxidizing solution is applied to generate a dielectric layer. A conductive layer is formed on the dielectric layer for fabricating semiconductor devices. 17-. (canceled)8. A method for fabricating semiconductor devices , the method comprising:providing a substrate including a first region and a second region;forming a first polymer layer on the first region and the second region;forming a second polymer layer on the first polymer layer;removing the second polymer layer on the first region;applying an oxygen-based plasma to remove the first polymer layer on the first region;applying an oxidizing solution to generate a first dielectric layer on the first region and to remove the second polymer layer and the first polymer layer on the second region; andforming a first conductive layer on the first dielectric layer for fabricating one or more first devices.9. The method of claim 8 , wherein the first conductive layer is used to fabricate a gate stack of a core device claim 8 , and the first dielectric layer serves as a gate dielectric of the core device.10. The method of claim 8 , wherein:a second dielectric layer is formed on the second region; anda second conductive layer is formed on the second dielectric layer for fabricating one or more second devices;wherein the first dielectric layer has a first thickness and the second dielectric layer has a second thickness different from the first thickness.11. The method of claim 10 , wherein the second conductive layer is used to fabricate a gate stack of an input/output device claim 10 , and the second dielectric layer serves as a gate dielectric of the input/output device.12. The method of claim 10 , wherein the first dielectric layer has a thickness of about 1 nm claim 10 , and the second dielectric layer ...

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Номер записи: 77
15-03-2018 дата публикации

SELECTIVE METAL OXIDE DEPOSITION USING A SELF-ASSEMBLED MONOLAYER SURFACE PRETREATMENT

Номер: US20180076027A1
Автор: Kang Hoyoung, Leusink Gerrit J., Tapily Kandabara N., Wajda Cory
Принадлежит:

Embodiments of the invention provide methods for selective film deposition using a surface pretreatment. According to one embodiment, the method includes providing a substrate containing a dielectric layer and a metal layer, exposing the substrate to a reactant gas containing a molecule that forms self-assembled monolayers (SAMs) on the substrate, and thereafter, selectively depositing a metal oxide film on a surface of the dielectric layer relative to a surface of the metal layer by exposing the substrate to a deposition gas. 1. A method of processing a substrate , comprising:providing a substrate containing a dielectric layer and a metal layer;exposing the substrate to a reactant gas containing a molecule that forms self-assembled monolayers (SAMs) on the substrate; andthereafter, selectively depositing a metal oxide film on a surface of the dielectric layer relative to a surface of the metal layer by exposing the substrate to a deposition gas.2. The method of claim 1 , wherein the metal layer contains Cu claim 1 , Al claim 1 , Ta claim 1 , Ti claim 1 , W claim 1 , Ru claim 1 , Co claim 1 , Ni claim 1 , or Mo.3. The method of claim 1 , further comprising oxidizing the surface of the metal layer prior to or during the exposing of the substrate to the reactant gas.4. The method of claim 1 , wherein the molecule includes a head group claim 1 , a tail group claim 1 , and a functional end group claim 1 , and wherein the head group includes a thiol claim 1 , a silane claim 1 , or a phosphonate.5. The method of claim 1 , wherein the molecule includes perfluorodecyltrichlorosilane (CF(CF)CHCHSiCl) claim 1 , perfluorodecanethiol (CF(CF)CHCHSH) claim 1 , chlorodecyldimethylsilane (CH(CH)CHSi(CH)Cl) claim 1 , or tertbutyl(chloro)dimethylsilane ((CH)CSi(Cl)(CH))).6. The method of claim 1 , wherein the metal oxide film contains HfO claim 1 , ZrO claim 1 , or AlO.7. The method of claim 1 , wherein a density of the SAMs is greater on the surface of the metal layer than on the ...

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Номер записи: 78
15-03-2018 дата публикации

DISPLAY DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE USING THE SAME

Номер: US20180076412A1
Автор: BAE Kyuhan, CHA Jaelok, JUNG Younhwan, KIM Kijong, Kim Min-Seop, Kim Minki, Kim Taesoo, KIM Younggu, Nam Yunoh
Принадлежит:

A display device includes a window member, a display module, a protective cover, and a coupling structure. The display module includes a non-bending area on a rear surface of the window member and a bending area bent from the non-bending area. The protective cover is on a rear surface of the display module to cover the bending area of the display module. The coupling structure couples the display module to the protective cover. The display module is coupled to other components of an electronic device after the protective cover is detached from the display module. 1. A display device comprising:a window member;a display module comprising a non-bending area overlapped with a display area of the window member and a bending area bent from the non-bending area;a protective cover on a rear surface of the display module to cover the bending area of the display module; anda coupling structure coupling the display module to the protective cover.2. The display device of claim 1 , wherein the coupling structure comprises a first adhesive member comprising a first adhesive surface attached to the display module and a second adhesive surface attached to the protective cover.3. The display device of claim 2 , wherein the first adhesive member comprises a first part overlapped with the protective cover and a second part extending from the first part and protruding outward from the window member when viewed in a plan view.4. The display device of claim 3 , wherein the first part comprises a base layer and first and second adhesive layers respectively on front and rear surfaces of the base layer claim 3 , and the second part comprises a base layer integrally formed with the base layer of the first part.5. The display device of claim 3 , wherein each of the first part and the second part comprises a base layer and first and second adhesive layers respectively on both front and rear surfaces of the base layer claim 3 , and the second part further comprises cover layers respectively on ...

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Номер записи: 79
24-03-2022 дата публикации

Method for manufacturing semiconductor device including air gap

Номер: US20220093387A1
Автор: Changwoo Seo, Dain LEE, Jinwon MA, Kyungwook Park, Suyoun SONG, Wonseok Yoo, Yoongoo Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.

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Номер записи: 80
05-03-2020 дата публикации

PECVD Tungsten Containing Hardmask Films And Methods Of Making

Номер: US20200075333A1
Автор: Cheng Rui, Mallick Abhijit Basu, Manna Pramit, Roy Susmit Singha
Принадлежит:

Methods of forming a tungsten film comprising forming a boron seed layer on an oxide surface, an optional tungsten initiation layer on the boron seed layer and a tungsten containing film on the boron seed layer or tungsten initiation layer are described. Film stack comprising a boron seed layer on an oxide surface with an optional tungsten initiation layer and a tungsten containing film are also described. 1. A stack comprising:a substrate having an oxide surface;a boron seed layer on the oxide surface;a tungsten initiation layer on the boron seed layer; anda tungsten containing film on the tungsten initiation layer, the tungsten containing film comprising tungsten carbide.2. The stack of claim 1 , wherein the boron seed layer has a thickness in the range of about 10 Å to about 200 Å.3. The stack of claim 2 , wherein the boron seed layer has a thickness in the range of about 10 Å to about 100 Å.4. The stack of claim 1 , wherein the tungsten initiation layer has a thickness in the range of about 10 Å to about 200 Å.5. The stack of claim 4 , wherein the tungsten initiation layer has a thickness in the range of about 10 Å to about 100 Å.6. The stack of claim 1 , wherein the tungsten initiation layer comprises substantially pure tungsten.7. The stack of claim 1 , wherein the tungsten containing film has a thickness greater than about 8000 Å.8. The method of claim 1 , wherein the tungsten containing film further comprises one or more of tungsten metal claim 1 , tungsten nitride claim 1 , tungsten boride claim 1 , or tungsten boronitride.9. The stack of claim 1 , wherein the boron seed layer and the tungsten initiation layer have a combined thickness less than about 150 Å.10. The stack of claim 9 , wherein the boron seed layer has a thickness of about 50 Å claim 9 , the tungsten initiation layer has a thickness of about 50 Å claim 9 , and the tungsten containing film has a thickness greater than about 8000 Å.11. The stack of claim 1 , wherein the substrate comprises ...

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Номер записи: 81
12-06-2014 дата публикации

Method for manufacturing semiconductor structure

Номер: US20140162431A1
Автор: Chih-Chung Chen, Keng-Jen Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
Принадлежит: United Microelectronics Corp

A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.

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Номер записи: 82
22-03-2018 дата публикации

Substrate processing apparatus and substrate processing method

Номер: US20180082831A1
Автор: Hisashi Kawano, Koji Kagawa, Meitoku Aibara, Yuki Yoshida
Принадлежит: Tokyo Electron Ltd

In order to remove from a substrate having a concavo-convex pattern formed on a surface of the substrate, a solid material with which a concave portion of the concavo-convex pattern is filled and which is formed by evaporating a solvent in a sublimable substance solution containing a sublimable substance that sublimates at a temperature equal to or higher than a first temperature, and an impurity that evaporates at a temperature equal to or higher than a second temperature that is higher than the first temperature, the prevent invention provides a substrate processing apparatus and a substrate processing method which heat the substrate to a temperature equal to or higher than the second temperature.

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Номер записи: 83
22-03-2018 дата публикации

Method of ONO Stack Formation

Номер: US20180083024A1
Автор: Krishnaswamy Ramkumar
Принадлежит: Cypress Semiconductor Corp

A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

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Номер записи: 84
14-03-2019 дата публикации

EPITAXIAL STRUCTURE OF N-FACE AlGaN/GaN, ACTIVE DEVICE, AND METHOD FOR FABRICATING THE SAME WITH INTEGRATION AND POLARITY INVERSION

Номер: US20190081165A1
Автор: Chih-Shu Huang
Принадлежит: Chih-Shu Huang

The present invention provides an epitaxial structure of N-face AlGaN/GaN, its active device, and the method for fabricating the same. The structure comprises a substrate, a C-doped buffer layer on the substrate, a C-doped i-GaN layer on the C-doped buffer layer, a i-Al y GaN buffer layer on the C-doped i-GaN layer, an i-GaN channel layer on the C-doped i-Al y GaN buffer layer, and an i-Al x GaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By using the p-GaN inverted trapezoidal gate or anode structure in device design, the 2DEG in the epitaxial structure of N-face AlGaN/GaN below the p-GaN inverted trapezoidal gate structure will be depleted. Then the 2DEG is located at the junction between the i-GaN channel layer and the i-Al y GaN layer, and thus fabricating p-GaN gate enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs).

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Номер записи: 85
24-03-2016 дата публикации

Semiconductor device and method for manufacturing same

Номер: US20160087028A1
Автор: Takakazu Matsui, Toshiyuki Hirota
Принадлежит: PS4 Luxco SARL

One semiconductor device includes a capacitor having a lower electrode which is arranged on a semiconductor substrate, a second protective film, a dielectric film which has a defect that extends in the film thickness direction from an upper surface that faces the second protective film, a third protective film which has at least a defect filling film that is formed of an insulating body filling the defect, a first protective film which covers the dielectric film and the third protective film, and an upper electrode which covers the first protective film.

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Номер записи: 86
23-03-2017 дата публикации

Substrate processing apparatus, substrate processing method and recording medium

Номер: US20170084480A1
Автор: Mitsuaki Iwashita, Nobutaka Mizutani, Takashi Tanaka
Принадлежит: Tokyo Electron Ltd

A substrate processing apparatus can remove, from a substrate having a copper wiring formed by a dry etching process using an organic etching gas, e.g., one or more kinds of organic etching gases selected from a methane gas, a CF-based gas, a carboxylic acid-based gas containing a methyl group and an alcohol-based gas, an organic polymer which is originated from the organic etching gas and generated in the dry etching process and adheres to a surface of the substrate. In a substrate processing apparatus 1 , a first processing unit 4 includes a first cleaning liquid supply unit 43 a configured to supply a first cleaning liquid L 1 selected from a chemical liquid containing hydrogen peroxide and a chemical liquid containing a polar organic solvent, and the first cleaning liquid L 1 is supplied onto a substrate W 1 from the first cleaning liquid supply unit 43 a.

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Номер записи: 87
19-06-2014 дата публикации

Silicon carbide semiconductor devices having nitrogen-doped interface

Номер: US20140167073A1
Автор: Michael MacMillan
Принадлежит: GLOBAL POWER DEVICE CO

Methods, systems, and devices are disclosed for implementing high power circuits and semiconductor devices. In one aspect, a method for fabricating a silicon carbide semiconductor device includes forming a thin epitaxial layer of a nitrogen doped SiC material on a SiC epitaxial layer formed on a SiC substrate, and thermally growing an oxide layer to form an insulator material on the nitrogen doped SiC epitaxial layer, in which the thermally grown oxide layer results in at least partially consuming the nitrogen doped SiC epitaxial layer in the oxide layer to produce an interface including nitrogen between the SiC epitaxial layer and the oxide layer.

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Номер записи: 88
25-03-2021 дата публикации

METHOD FOR FORMING BORON-BASED FILM, FORMATION APPARATUS

Номер: US20210090888A1
Автор: Ikuta Hiroyuki, LI Jinwang, Oka Masahiro, Ueda Hirokazu, Watanabe Yoshimasa, Yamamoto Yuuki
Принадлежит:

A method of forming a boron-based film mainly containing boron on a substrate includes forming, on the substrate, an adhesion layer containing an element contained in a surface of the substrate and nitrogen, and subsequently, forming the boron-based film on the adhesion layer. 1. A boron-based film formation method of forming a boron-based film mainly containing boron on a substrate , the method comprising:forming, on the substrate an adhesion layer including an element contained in a surface of the substrate and nitrogen; andsubsequently, forming the boron-based film on the adhesion layer.2. The boron-based film formation method of claim 1 , wherein the adhesion layer is formed to have a thickness of 100 nm or less.3. The boron-based film formation method of claim 1 , wherein the boron-based film is a boron film including boron and inevitable impurities.4. The boron-based film formation method of claim 1 , wherein the substrate contains silicon provided on a surface of the substrate claim 1 , and the adhesion layer includes the silicon and the nitrogen.5. The boron-based film formation method of claim 4 , wherein the adhesion layer is one selected from a group consisting of SiN claim 4 , Si—N:H claim 4 , Si—C—N claim 4 , Si—B—N claim 4 , and Si—O—N.6. The boron-based film formation method of claim 1 , wherein the forming the adhesion layer is performed through a CVD or an ALD.7. The boron-based film formation method of claim 6 , wherein the forming the adhesion layer is performed using a processing gas composed of a gas including the element contained in the surface of the substrate and a gas containing the nitrogen.8. The boron-based film formation method of claim 6 , wherein the forming the adhesion layer is performed through a plasma CVD or a plasma ALD.9. The boron-based film formation method of ; wherein the forming the adhesion layer is performed using a processing gas composed of a gas including the element contained in the surface of the substrate and a gas ...

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Номер записи: 89
25-03-2021 дата публикации

Semiconductor Structure with Staggered Selective Growth

Номер: US20210090944A1
Автор: Teng-Chun Tsai, Wei-Hao Wu, Zhi-Chang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

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Номер записи: 90
29-03-2018 дата публикации

Method for forming dielectric film and method for fabricating semiconductor device

Номер: US20180090313A1
Автор: Sun Hye Hwang, Won Woong CHUNG, Youn Joung CHO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of forming a dielectric film includes providing a substrate in a chamber, and forming a silicon nitride film on the substrate using an atomic layer deposition (ALD) method in which a first gas including a silicon precursor containing hexachlorodisilazane (HCDZ) and a second gas containing a nitrogen ingredient are introduced into the chamber.

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Номер записи: 91
29-03-2018 дата публикации

PROCESS FOR FABRICATING SILICON NANOSTRUCTURES

Номер: US20180090568A1
Автор: BLACK Marcie R., Buchine Brent A., Modawar Faris
Принадлежит:

A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and contacting the metallized substrate with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent. 1. A nanostructured array comprising polycrystalline silicon, wherein the nanostructures of the array have lengthwise directions disposed at a non-zero angle to a silicon-containing substrate, wherein the array is formed by etching a substrate composed primarily of polycrystalline silicon. This application claims priority under 35 U.S.C. § 121 as a division of U.S. patent application Ser. No. 14/924,273, filed Oct. 27, 2015, titled “PROCESS FOR FABRICATING SILICON NANOSTRUCTURES,” which is a continuation of U.S. patent application Ser. No. 14/444,361, filed Jul. 28, 2014, titled “PROCESS FOR FABRICATING NANOWIRE ARRAYS,” now U.S. Pat. No. 9,202,868, which is a continuation of U.S. patent application Ser. No. 13,305,649, filed Nov. 28, 2011, titled “NANOSTRUCTURED SILICON FOR BATTERY ANODES,” now U.S. Pat. No. 8,791,449, which is a continuation of U.S. patent application Ser. No. 12/423,623, filed Apr. 14, 2009, titled “PROCESS FOR FABRICATING NANOWIRE ARRAYS,” now U.S. Pat. No. 8,143,143, which claims priority to U.S. Provisional Applications Nos. 61/044,573, filed Apr. 14, 2008, and 61/141,082, filed Dec. 29, 2008. These applications are incorporated by reference herein.This application pertains to the field of nanotechnology.The ability to structure and pattern silicon is important for many applications. There has been particular interest in patterning silicon to make nanostructures. Relevant information regarding silicon fabrication processes known to those of skill in the art can be found, for example, in Sami Franssila, (John Wiley & Sons, 2004), and the references cited there.Semiconductor nanowires have become the focal point of research over the last decade due to ...

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Номер записи: 92
21-03-2019 дата публикации

EMBEDDED SONOS WITH TRIPLE GATE OXIDE AND MANUFACTURING METHOD OF THE SAME

Номер: US20190088487A1
Автор: Keshavarzi Ali, Kouznetsov Igor, Prabhakar Venkatraman, Ramkumar Krishnaswamy
Принадлежит: CYPRESS SEMICONDUCTOR CORPORATION

A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness. 120-. (canceled)21. A memory device , comprising:a non-volatile memory (NVM) transistor including a charge-trapping layer and a blocking dielectric having a dielectric thickness;a first field-effect transistors (FET) including a first gate oxide of a first thickness, wherein the first gate oxide includes three sublayers;a second FET including a second gate oxide of a second thickness; anda third FET including a third gate oxide of a third thickness;wherein the first thickness is greater than the second thickness and the second thickness is greater than the third thickness, and wherein a first sublayer of the first gate oxide has a first sublayer thickness independent of the dielectric thickness, and a second sublayer of the first gate oxide has a second sublayer thickness corresponding to the dielectric thickness.22. The memory device of claim 21 , wherein the NVM transistor and the first claim 21 , second claim 21 , and third FETs are disposed in a single integrated circuit package.23. The memory device of claim 21 , wherein the first and second sublayers and a third sublayer of the first gate oxide are each formed in a separate oxidation step claim 21 , and wherein the first sublayer thickness is independent of the second and third thicknesses.24. The memory device of claim 21 , wherein the second sublayer thickness is ...

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Номер записи: 93
05-05-2022 дата публикации

New precursors for selective atomic layer deposition of metal oxides with small molecule inhibitors

Номер: US20220139703A1
Автор: Bent Stacey F., Oh Il-Kwon, Yarbrough Josiah
Принадлежит:

Improved selective atomic layer deposition of metal oxides is provided that has large-ligand (i.e., molecular weight >20) metal precursors. A small molecule inhibitor on non-growth surfaces is used to distinguish growth surfaces from non-growth surfaces. This approach does not rely on formation of a self-assembled monolayer on the non-growth surfaces.

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Номер записи: 94
30-03-2017 дата публикации

METHOD FOR MANUFACTURING SILICA LAYER, SILICA LAYER, AND ELECTRONIC DEVICE

Номер: US20170092488A1
Автор: Bae Jin-Hee, LEE Jiho, LIM Wanhee, Noh Kunbae, Yun Huichan
Принадлежит:

A method of manufacturing a silica layer includes: coating a pre-wetting liquid material including a carbon compound on a substrate; coating a composition for forming a silica layer on the substrate coated with the pre-wetting liquid material; and curing a substrate coated with the composition for forming a silica layer. 1. A method of manufacturing a silica layer , the method comprising:coating a pre-wetting liquid material comprising a carbon compound on a substrate;coating a composition for forming a silica layer on the substrate coated with the pre-wetting liquid material; andcuring a substrate coated with the composition for forming a silica layer.2. The method of claim 1 , wherein the carbon compound comprises a substituted or unsubstituted benzene ring in the structure and the total number of carbon atoms of the carbon compound is 6 to 14.3. The method of claim 1 , wherein the carbon compound has a boiling point of about 98° C. to about 200° C.4. The method of claim 1 , wherein the carbon compound comprises a substituted or unsubstituted trimethylbenzene claim 1 , a substituted or unsubstituted dimethylbenzene claim 1 , a substituted or unsubstituted diethylbenzene claim 1 , or a combination thereof.5. The method of claim 1 , wherein the composition for forming a silica layer comprises a silicon-containing polymer and a solvent.6. The method of claim 5 , wherein the silicon-containing polymer comprises polysilazane claim 5 , polysiloxazane claim 5 , or a combination thereof.7. The method of claim 5 , the solvent comprises at least one selected from benzene claim 5 , toluene claim 5 , xylene claim 5 , ethylbenzene claim 5 , diethylbenzene claim 5 , trimethylbenzene claim 5 , triethylbenzene claim 5 , cyclohexane claim 5 , cyclohexene claim 5 , decahydro naphthalene claim 5 , dipentene claim 5 , pentane claim 5 , hexane claim 5 , heptane claim 5 , octane claim 5 , nonane claim 5 , decane claim 5 , ethylcyclohexane claim 5 , methylcyclohexane claim 5 , p- ...

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Номер записи: 95
30-03-2017 дата публикации

Selective silicon dioxide deposition using phosphonic acid self assembled monolayers as nucleation inhibitor

Номер: US20170092533A1
Автор: David Thompson, Eswaranand VENKATASUBRAMANIAN, Mark Saly, Prerna Sonthalia Goradia, Rana HOWLADER, Robert Jan Visser, Tapash Chakraborty
Принадлежит: Applied Materials Inc

Methods of selectively depositing a patterned layer on exposed dielectric material but not on exposed metal surfaces are described. A self-assembled monolayer (SAM) is deposited using phosphonic acids. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the exposed metal portion and the tail moiety extending away from the patterned substrate and reducing the deposition rate of the patterned layer above the exposed metal portion relative to the deposition rate of the patterned layer above the exposed dielectric portion. A dielectric layer is subsequently deposited by atomic layer deposition (ALD) which cannot initiate in regions covered with the SAM in embodiments.

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Номер записи: 96
30-03-2017 дата публикации

Method and apparatus for dynamic control of the temperature of a wet etch process

Номер: US20170092550A1
Автор: Antonio Luis Pacheco Rotondaro, Wallace P. Printz
Принадлежит: Tokyo Electron Ltd

A method for controlling the temperature profile of phosphoric acid process over a wafer surface through the dynamic control of radial dispensing of sulfuric acid at a selected temperature, which includes providing a substrate with a layer formed thereupon; dispensing a first chemical and second chemicals onto the layer while adjusting at least one parameter of the second chemical dispense to vary the etch rate across a region of the substrate.

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Номер записи: 97
30-03-2017 дата публикации

Activated thin silicon layers

Номер: US20170092725A1
Автор: John Rozen, Martin M. Frank, Takashi Ando, Vijay Narayanan
Принадлежит: International Business Machines Corp

A method for forming a layer of material on a silicon layer comprises depositing a layer of silicon material having a hydrophobic H-terminated surface on a substrate, forming a hydrophilic seed layer on the surface of the silicon material, and depositing an oxide material layer on the hydrophilic seed layer.

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Номер записи: 98
05-04-2018 дата публикации

CHEMICALLY PATTERNED GUIDE LAYERS FOR USE IN CHEMOEPITAXY DIRECTING OF BLOCK CO-POLYMERS

Номер: US20180096838A1
Автор: Dai Jinhua, Lowes Joyce
Принадлежит:

The present invention is broadly concerned with materials, processes, and structures that allow an underlayer to be imaged directly using conventional lithography, thus avoiding the photoresist processing steps required by prior art directed self-assembly (DSA) processes. The underlayers can be tailored to favor a selected block of the DSA block co-polymers (BCP), depending on the pattern, and can be formulated either to initially be neutral to the BCP and switch to non-neutral after photoexposure, or can initially be non-neutral to the BCP and switch to neutral after exposure. These materials allow fast crosslinking to achieve solvent resistance and possess good thermal stability. 2. The method of claim 1 , wherein said initial surface property comprises an initial surface energy and the altered surface property comprises an altered surface energy that is different from said initial surface energy.3. The method of claim 2 , wherein:the dispersive and polar components of said initial surface energy are from about 33 dyne/cm to about 41 dyne/cm and from about 3 dyne/com to about 10 dyne/cm, respectively; andthe dispersive and polar components of said altered surface energy are from about 25 dyne/cm to about 36 dyne/cm and from about 8 dyne/cm to about 13 dyne/cm, respectively.4. The method of claim 1 , wherein:said initial surface property is a lack of affinity towards one of said first and second blocks over the other of said first and second blocks; andduring said exposing, an affinity to one of said first and second blocks over the other of said first and second blocks develops, said affinity being the altered surface property.5. The method of claim 4 , wherein said affinity is towards the first block claim 4 , and during said causing the first block assembles and forms said first self-assembled region at said altered surface property.6. The method of claim 4 , wherein said patternable layer comprises a polymer dispersed or dissolved in a solvent system claim 4 , ...

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Номер записи: 99
01-04-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20210098252A1
Автор: ONOZAWA Yuichi
Принадлежит: FUJI ELECTRIC CO., LTD.

A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 μm. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode. 1. A diode comprising:an n-type drift layer provided in an n-type semiconductor substrate;a p-type anode layer provided in a first main surface of the semiconductor substrate;an n-type cathode layer provided in a second main surface of the semiconductor substrate; anda plurality of n-type buffer layers provided between the drift layer and the cathode layer, the buffer layers including hydrogen as a donor, wherein a shallowest buffer layer formed on a further inner side of the semiconductor substrate than the cathode layer,', 'an intermediate buffer layer formed on a further inner side of the semiconductor substrate than the shallowest buffer layer, and', 'a deepest buffer layer formed in a position deeper than 15 μm from the second main surface of the semiconductor substrate and on a further inner side of the semiconductor substrate than the intermediate buffer layer,, 'the buffer layers comprisewherein a distribution of a carrier concentration of the semiconductor substrate has a peak and a tail, of which the carrier concentration is lower than that of the peak, in each of the shallowest buffer layer, the intermediate buffer layer and the deepest buffer layer,wherein the tail of the ...

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Номер записи: 100