NEUROMORPHIC DEVICE INCLUDING SYNAPSE HAVING MULTIPLE SYNAPSE CELLS
The present invention refers to neuro morphics associated therewith element relates to search, in particular having a plurality of synaptic cells including neuro morphics associated therewith are disclosed element occurs. Recent techniques mimicking the human brain morphics associated therewith neurotrophin in the spotlight disclosed. Neurotrophin - synaptic neurons in a prepaid technique morphics associated therewith, a plurality of post - synaptic neurons, and a plurality of synapse comprising the. The neurotrophin morphics associated therewith neurotrophin morphics associated therewith in accordance with the state learned element exist various levels, size, or time according to outputs pulse or spike. The present invention includes a plurality of synaptic cells if the number and having a number element including neurotrophin or hypermetropia morphics associated therewith for the study. The present invention is if the number and different current driving efficiency synaptic cells including neurotrophin number element morphics associated therewith are disclosed. The present invention includes a plurality of synaptic cells if the number and the number one synapse can be used as an element or hypermetropia morphics associated therewith neurotrophin. The present invention if the number to one or more various pipeline and number and number are not, another and number are not referred to below per provider may be clearly understand from the substrate are disclosed. In the embodiment of the present invention pre-element by neurotrophin - one morphics associated therewith is faster circuit; post - is faster circuit; and said free - - is faster circuit and said post and electrically connected to the circuit is faster a synapse can be. Said plurality of row lines is connected to the pre - through said each synapse is faster and a common column line through said post - plurality of synaptic cells is faster circuit can be electrically connected. Said plurality of synaptic cells each include at least one transistor and at least one include disclosed. Said one synapse included in said plurality of synaptic cells may have different current driving transistors are the efficiency. Said transistors are, each, can be electrically connected to said plurality of row lines. The drain electrodes of said transistors, respectively, said plurality of row lines can be electrically connected. Said pixel electrodes are, respectively, can be electrically connected to corresponding said . Said plurality of said row lines and said each can be electrically connected with the drain electrodes of transistors. Said common column line and electrically connected to said pixel electrodes are connected to the edifice. Said transistor gate electrodes, respectively, said plurality of row lines can be electrically connected. The drain electrodes of said transistors, respectively, and electrically connected to the voltage generator can be. Said plurality of synaptic cells, each, can be different numbers of transistors. The same synaptic cell said said transistors can be connected in parallel with each other. Said that the gates of said common electrodes are the same synaptic cell can be electrically connected. Said transistor gate electrodes, respectively, said row lines connected to said synapse cell can be commonly connected. The drain electrodes of transistors said voltage generator can be electrically connected. Said plurality of synaptic cells, each, comprising transistor and can be. Said each synapse cells [su carrying on shoulder said fixed resistor values may have different tone. In the embodiment of the present invention pre-element by neurotrophin - one morphics associated therewith is faster circuit; post - is faster circuit; and said free - - is faster circuit and said post and electrically connected to the circuit is faster a synapse can be. The synapse said different current driving efficiency can be a plurality of synaptic cells. Said plurality of synaptic cells, each, comprising transistor and can be. Said each synapse cell may have different channel size said each transistor. Said plurality of synaptic cells, each, comprising different numbers of transistors and one can be. Said plurality of synaptic cells, each, comprising transistor and can be. Each synapse cell said each said fixed resistor may have different values. Said plurality of synaptic cells are a plurality of row lines independently from other said pre - is faster circuit can be electrically connected, and common column line through said post and electrically connected to the circuit is faster - commonly can be. Other embodiment examples which the described and drawing specific are obviated included in the nanometer range. The technical idea of the present invention the output of each synapse next synapse using one cell than the technique is turned on if the data for the study and implementing techniques for their use in 2000. The technical idea of the present invention can be determined in advance and stored is written to the study of this circuit does not need the learning process, the data can be written and stored. The technical idea of the present invention according to a multi-level data storage applications more versatile synaptic cells can. The technical idea of the present invention digitally converts sap102 structure utilizes an electron structure than if neuro morphics associated therewith element is implemented for the rest disclosed. In the embodiment of the present invention may be provided with various other referred in body effects are not referred to will. Figure 1 shows a general outline of the present invention the timing block diagram illustrating this element by neuro morphics associated therewith also one in the embodiment disclosed. Figure 2 shows a general outline of the present invention also one in the embodiment morphics associated therewith for synaptic detail the timing diagram illustrating blocks by neurotrophin are disclosed. In the embodiment of the present invention is also 3a to 3e may be provided with a plurality of synaptic cells with synaptic are various general outline are shown in block diagram illustrating the are disclosed. In the embodiment of the present invention is 4 to 7 also may be provided with a plurality of synaptic cells with a variety of synapse are shown in block diagram illustrating the general outline are disclosed are morphics associated therewith neurotrophin. Figure 8 shows a general outline of the present invention also one in the embodiment the timing block diagram illustrating this element by neuro morphics associated therewith 2000. Figure 9 shows a general outline of the present invention also one in the embodiment morphics associated therewith for synaptic detail the timing diagram illustrating blocks by neurotrophin are disclosed. In the embodiment of the present invention is also 10 and 11 may be provided with a general outline of the various elements are shown in block diagram illustrating this morphics associated therewith neurotrophin for their use in 2000. Figure 7 shows a general outline of the present invention also one in the embodiment according to the pattern recognition system timing block diagram illustrating this disclosed. Figure 12 shows a general outline of the present invention also one in the embodiment according to the pattern recognition system timing block diagram illustrating this disclosed. Advantages and features of the present invention, achieve the appended drawing method and an electronic component connected to the embodiment with specifically carry activitycopyright will reference the example. However in the present invention refers to hereinafter disclosure limited to the embodiment example but can be embodied in the form of various different, only the embodiment of the present invention disclosure is completely to examples, the present invention in the field of the invention is provided for alerting the person with skill in the art to which ball number which completely categories, defined by category of the present invention refers to claim only disclosed. The specification the term used in the present invention embodiment examples which account for a relayed number that is even endured. In the specification, a plurality type comprises a unit in a single may be phrase will not specially mentioned. Used in specification 'includes (comprises)' and/or 'including (comprising)' handle components, steps, operation and/or element comprises at least one other components, steps, operation and/or devices does not number the presence or addition times. One component other element (elements) 'connected' or '(connected to) coupled (coupled to)' is referred to as the, another element when coupled or connected between another element comprising both interposed intermediate or foreseeable. While, one component other element 'is directly connected (directly connected to) directly coupled (directly coupled to)' or " is another element is not interposed intermediate referred by a goniophotometer. 'And/or' handle items all and at least one each of a combination. In addition, the specification of the present invention ideal example cross-sectional drawing and/or discussed embodiment examples are described reference will that excels in plane view. Substrate in drawing, description and technical content of effective for exaggerated thickness regions are disclosed. The, number bath techniques and/or tolerances of form can be modified by example degrees. The, specific examples of the present invention embodiment shown is one which is produced according to the process for preparing the type number number including variations are disclosed. For example, right angle region is shown having an predetermined angular or round may be in the form disclosed. The, drawing exemplified regions are coarse has attribute, for example the shape for drawing exemplified areas in the region of the invention which form relayed number categories for endured. Professional specification over the same references refer to the same components. The, same references or similar references are read pipeline or drawing was not described, can be described with reference to another drawing. In addition, references is displayed was not, other drawing reference can be described. Figure 1 shows a general outline of the present invention the timing block diagram illustrating this element by neuro morphics associated therewith also one in the embodiment disclosed. The reference also 1, in the embodiment of the present invention is faster (neuromorphic device) includes a pre - morphics associated therewith element by neurotrophin one neuron circuit (10) (pre-a synaptic neuron circuit), neuron circuit is faster post - (20) (post-a synaptic neuron circuit), and mth synapse (30) comprising (synapses) can be. Mth synapse (30) is faster pre - neuronal circuit (10) extending in the row direction from row lines (R) (row lines) is faster and post - neuronal circuit (20) extending from the column direction (column lines) can be disposed at the intersection of column lines (C). One synapse (30) includes a plurality of row lines (R) and a column line (C) can be electrically connected. Is faster pre - neuronal circuit (10) includes a learning mode (learning mode), reset mode (reset mode), or reading mode (reading mode) through (R) low lines mth synapse (30) can be electrically transmitting pulses (pulses). Post is faster - neuronal circuit (20) includes a learning mode or reset mode (C) mth synapse through column lines (30) to transmit an electrical pulse that can be, and reading mode (C) column lines through mth synapse (30) can be electrical receiving pulses from. Mth synapse (30) having a multi-resistance level of a variable resistance element can be. In the embodiment of the present invention Figure 2 shows a one by neuro morphics associated therewith also of synapse (30) general outline block diagram illustrating detail the timing are disclosed. The reference 2 also, in the embodiment of the present invention one by neuro morphics associated therewith for synapse (30) includes a plurality of synaptic cells comprising (SC1 provided SCn) can be. A plurality of synaptic cells (SC1 provided SCn) each have a plurality of pre - synapse circuits (10 1 _ provided _n 10) and a plurality of row lines (R1 a-Rn) can be electrically connected through. A plurality of synaptic cells (SC1 provided SCn) can be commonly connected one column line (C). I.e., a plurality of synaptic cells (SC1 provided SCn) one synapse (30) can be constituting. Each synapse cells (SC1 provided SCn) can be storing different amount. For example, each synapse cells through common post - (SC1 provided SCn) is faster circuit (20) may have semiconductor device including the output AC, the synapse (30) capable of various information. Learning mode (learning mode) or in write mode (writing mode), is faster circuits pre - (1 _ 10 provided _n 10) corresponding each synaptic cells (SC1 provided SCn) can be independently learning or for writing data. In reading mode (reading mode), synaptic cells in common post - (SC1 provided SCn) data at the same time is faster circuit (20) can be output. I.e., each synapse cells (SC1 provided SCn) is summed with the currents are outputted from the common post - is faster circuit (20) can be output. Common post - is faster circuit (20) includes a synapse cells (SC1 provided SCn) total current value output from sensing or integration can be an information values and outputs. In the embodiment of the present invention may be provided with a plurality of synaptic cells 3a to 3e also includes various (SC1 provided SCn) synaptic are having (30a - 30n) are shown in the block diagram illustrating a general outline are disclosed. The reference also 3a to 3e, in the embodiment of the present invention may be provided with various mth synapse (30a - 30n) includes a plurality of synaptic cells comprising (SC1 provided SCn) can be. Each synapse cells (SC1 provided SCn) [su carrying on shoulder and a transistor (T1 a-Tn) (M1 a-Mn) can be. Transistors (T1 a-Tn) may have a different channel size and current driving efficiency (current driving efficiency). Specifically, number 1 transistor (T1) includes a basic channel size and base current drive efficiency may have, number 2 transistor (T1) (T2) is twice as channel size and number 1 transistor may have current driving efficiency. Number 3 transistor (T3) (T2) is twice as channel size and number 2 transistor may have current driving efficiency. Number 4 transistor (T4) is twice as channel size and current drive efficiency number 3 transistor (T3) may have. Number 5 transistor (T5) is twice as channel size and current drive efficiency number 4 transistor (T4) may have. The, second transistor includes a second transistor (Tn-a 1) n (Tn) n-a 1 may have twice as channel size and current drive efficiency. I.e., transistor (T1) fundamental channel size W assuming referred to as number 1, number 2 transistor (T2) is 2W may have channel size, number 3 transistor (T3) is 4W channel may have size, number 4 transistor (T4) is 8W channel may have size, number 5 transistor (T5) is channel size 16W may have, and n the second transistor (Tn) (2N -1 ) Channel size W may have. For example, channel size ratio of the width of the channel length of the channel, i.e. channel length of the channel divided by width can be defined. [Su carrying on shoulder (M1 a-Mn) may have fixed resistance or variable resistance. In one in the embodiment, the capacitor may be filled [su carrying on shoulder (M1 a-Mn). In the embodiment of the present invention in other, transistors (T1 a-Tn) may have the same channel size and current drive efficiency, and [su carrying on shoulder (M1 a-Mn) may have different fixed resistor values. , the synaptic cells (SC1 provided SCn) can be different current output values. In addition, in the embodiment of the present invention in other, [su carrying on shoulder (M1 a-Mn) may have plurality of fixing these resistors are connected in parallel. The, [su carrying on shoulder (M1 a-Mn) may have different total resistance values, and the different current output values synaptic cells (SC1 provided SCn) can be. Synaptic cells (SC1 provided SCn) and are each independently may be written, read and simultaneously can be disclosed. For example, synaptic cells (SC1 provided SCn) is faster circuits are each independently pre - (1 _ 10 provided _n 10) and because, data can be written independently. Specifically, mth synapse (30, 30a - 30n) software written and stored data to one side can be predetermined, determined data each mth synapse (30, 30a - 30n) of synaptic cells (SC1 provided SCn) can be independently written and stored in. The, synaptic cells (SC1 provided SCn) not subjected the connection structure. In addition, common column line (C) is powered on at the same time turn - synaptic cells (SC1 provided SCn) can output data. Specifically, each output is summed with the current values (SC1 provided SCn) synaptic cells with a common post - is faster circuit (20) can be output. The reference 3a also, in the embodiment of the present invention one by synapse (30a) includes a first stage information levels may have. Specifically, number 1 transistor (T1) and (T2) number 2 transistor are each independently on/off output current by synaptic cells (SC1 - SC2) can be the first stage levels may have. Number 1 transistor (T1) and (T2) according to a combination of on/off state current levels table 1 number 2 transistor has been described. The 3b also refers, in the embodiment of the present invention one by synapse (30b) is eight steps may have information levels. Specifically, number 1 transistor (T1), (T2) transistor number 2, number 3 on/off transistor (T3) and each independently capable of AC output by synaptic cells (SC1 - SC3) may have eight step information levels. Number 1 transistor (T1), (T2) transistor number 2, number 3 transistor (T3) on/off state according to a combination of current levels and to table 2 is disclosed. Current level 0 to 3 (T3) is in an off state and it may number 3 transistor, the reference can be to understand the table 1. Similarly, the reference also 3c to 3e, in the embodiment of the present invention may be provided with various mth synapse (30c - 30n) according to a number of the transistors is 2 (Tn)n Step information levels may have. (N is a positive integer) specifically, two transistors (T1 - T2) (SC1 - SC2) including two synaptic cells having a synaptic (30a) is 22 Step information levels=4 may have, three transistors (T1 - T3) with three synaptic cells (SC1 - SC3) including a synaptic (30b) is 23 Step information may have levels=8, four transistors (T1 - T4) (SC1 - SC4) including four synaptic cells with a synaptic (30c) is 24 Step information levels=16 may have, the five transistors (T1 - T5) with the five synaptic cells (SC1 - SC5) including a synaptic (30d) is 25 Step information levels=32 may have, and n with n of transistors (T1 a-Tn) of synaptic cells (SC1 provided SCn) including a synaptic (30n) is 2(N-a 1) Step information levels may have. Illustratively, number 1 to number 4 transistors (T1 - T4) according to a combination of on/off state current levels table 3 has been described. In the case of table 1 and table 2 number 4 transistor (T4) is in an off state at a data input has been omitted. Five or more transistors (T1 a-Tn) (SC1 provided SCn) examples of synaptic cells having current versus level is supplied thereto. In the embodiment of the present invention may be provided with a neurotrophin 4 also to Figure 7 shows a mth synapse elements also various general outline block diagram illustrating the passing of timing morphics associated therewith are disclosed. In the embodiment of Figure 4 of the present invention one morphics associated therewith by neurotrophin synaptic (30) is connected to row lines (R1 a-Rn) [su carrying on shoulder (M1 a-Mn) and common column line (C) comprising (T1 a-Tn) can be connected to the transistors. I.e., also shown in 3a to 3e mth synapse (30a - 30n) compared, transistors (T1 a-Tn) (M1 a-Mn) can be of [su carrying on shoulder and that its position changes. I.e., also shown in 3a to 3e mth synapse (30a - 30n) of the technical idea of Figure 4 synapse (30) can be applied. The reference also 5, in the embodiment of the present invention one by synapse (30) includes a plurality of synaptic cells comprising (SC1 provided SCn) can be, each synapse cells (SC1 provided SCn) comprises at least one transistors (T1 a-Tn) and a [su carrying on shoulder can be a (M1 a-Mn). Specifically, the different numbers of transistors synaptic cells (SC1 provided SCn) comprising (T1 a-Tn) can be. For example, synaptic cell (SC1) number 1 (T1) include one transistor (M1) and a [su carrying on shoulder and, number 2 (SC2) (T1, T2) synaptic cell comprising two transistors and a [su carrying on shoulder (M2) can be, and n the second synaptic cell (SCn) n (T1 a-Tn) (Mn) comprising two transistors and a [su carrying on shoulder can be. In the embodiment of the present invention in one, transistors (T1 a-Tn) may have the same channel size and current drive efficiency. Thus, according to a number of the transistors (T1 a-Tn) synaptic cells (SC1 provided SCn) having various current levels can be delivering currents. Transistors (T1 a-Tn) can be connected in parallel. The same synapse cells (SC1 provided SCn) of gate electrodes are electrically connected to each other transistors (T1 a-Tn) can be. I.e., the same synapse cells (SC1 provided SCn) transistors (T1 a-Tn) at the same time turned on and - off - can be. The reference also 6, in the embodiment of the present invention one by synapse (30) and includes a plurality of synaptic cells include (SC1 provided SCn), each synapse cells (SC1 provided SCn) potential transistors (Tf1 provided Tfn), [su carrying on shoulder (M1 a-Mn), and comprising a back transistors (Tr1 non-Trn) can be. Potential transistors (Tf1 provided Tfn) low lines of drain electrodes (R1 a-Rn) is faster circuits through pre - (1 _ 10 provided _n 10) can be connected respectively in electrical, and source electrodes are common column line (C) back transistors (Tr1 non-Trn) through common post - is faster circuit (20) can be electrically connected. 3A to 3e also refers to, different channel size and current drive efficiency potential transistors (Tf1 provided Tfn) may have, and back transistors (Tr1 non-Trn) also may have different channel size and current drive efficiency. The same synapse cells (SC1 provided SCn) potential transistors (Tf1 provided Tfn) and of gate electrodes are connected to each other is set back transistors (Tr1 non-Trn) can be. I.e., the same synapse cells (SC1 provided SCn) potential transistors (Tf1 provided Tfn) and at the same time turn - on and - back transistors (Tr1 non-Trn) can turn off disclosed. The reference also 7, in the embodiment of the present invention one by synapse (30) and includes a plurality of synaptic cells include (SC1 non-SC), each synapse cells (SC1 provided SCn) comprises at least one potential transistor (Tf1 provided Tfn), one [su carrying on shoulder (M1 a-Mn), a back and at least one transistor (Tr1 non-Trn) can be. The idea is to 5 and 6 in the embodiment also may be understood to reference surface in particular also are disclosed. Figure 8 shows a general outline of the present invention also one in the embodiment the timing block diagram illustrating this element by neuro morphics associated therewith 2000. The reference also 8, one of the present invention in the embodiment of Figure 1 neurotrophin in the host by neuro morphics associated therewith element morphics associated therewith, mth synapse (30) further comprises a reference voltage (Vr) and electrically connected to the nodes can be. Reference voltage nodes (Vr) (Vdd: power voltage) or ground voltage comprising voltage (Vss: ground voltage) can be. In the embodiment of the present invention also by neuro morphics associated therewith for one Figure 9 shows a synaptic (30) general outline block diagram illustrating detail the timing are disclosed. The reference also 9, in the embodiment of the present invention one by neuro morphics associated therewith for synapse (30) is of Figure 2 synapse (30) compared to the, each synapse cells (SC1 provided SCn) comprising units electrically connected with the reference voltage nodes (Vr1 provided Vrn) can be. In the embodiment of the present invention 10 and 11 may be provided with a neurotrophin morphics associated therewith also the various mth synapse elements (30) to a general outline shown block diagram illustrating this disclosed. The reference also 10, in the embodiment of the present invention one by neuro morphics associated therewith for synapse (30) of the transistors (T1 a-Tn) synaptic cells (SC1 provided SCn) [su carrying on shoulder and comprising (M1 a-Mn) can be. Transistors (T1 a-Tn) low lines of gate electrodes are pre - (R1 a-Rn) is faster circuits through (1 _ 10 provided _n 10) can be electrically connected. Transistors (T1 a-Tn) are respectively electrically connected to the drain electrode of the voltage generator (Vr1 provided Vrn) can be. The source electrodes of transistors (T1 a-Tn) are respectively electrically connected with electrodes of number 1 [su carrying on shoulder (M1 a-Mn) can be. [Su carrying on shoulder (M1 a-Mn) electrodes are common column line (C) of number 2 through common post - is faster circuit (20) can be electrically connected. The, transistors (T1 a-Tn) on/off reference voltages nodes from each current supply (M1 a-Mn) [su carrying on shoulder (Vr1 provided Vrn) can be. Or, transistors (T1 a-Tn) on/off (M1 a-Mn) [su carrying on shoulder along each current from the reference voltage nodes (Vr1 provided Vrn) can be evacuated. In the embodiment of the present invention in other, transistors (T1 a-Tn) (M1 a-Mn) [su carrying on shoulder and position may be altered disclosed. Further reference to also 3a to 3e, transistors (T1 a-Tn) may have different channel size and current drive efficiency. Further reference to fig. 4, transistors (T1 a-Tn) (M1 a-Mn) [su carrying on shoulder and position may be altered disclosed. The reference also 11, in the embodiment of the present invention one by neuro morphics associated therewith for synapse (30) at least one transistor (T1 a-Tn) of synaptic cells (SC1 provided SCn) each comprising and a [su carrying on shoulder (M1 a-Mn) can be. For example, synaptic cell (SC1) number 1 (T1) include one transistor (M1) and a [su carrying on shoulder and, number 2 (SC2) (T1, T2) synaptic cell comprising two transistors and a [su carrying on shoulder (M2) can be, and n the second synaptic cell (SCn) n (T1 a-Tn) (Mn) comprising two transistors and a [su carrying on shoulder can be. In the embodiment of the present invention in one, transistors (T1 a-Tn) may have the same channel size and current drive efficiency. Thus, according to a number of the transistors (T1 a-Tn) synaptic cells (SC1 provided SCn) having various current levels can be delivering currents. Transistors (T1 a-Tn) can be connected in parallel. The same synapse cells (SC1 provided SCn) of gate electrodes are electrically connected to each other transistors (T1 a-Tn) can be. I.e., the same synapse cells (SC1 provided SCn) transistors (T1 a-Tn) at the same time turned on and - off - can be. Transistors (T1 a-Tn) are respectively electrically connected to the drain electrode of the voltage generator (Vr1 provided Vrn) can be, the source electrodes of transistors (T1 a-Tn) are respectively electrically connected with electrodes of number 1 [su carrying on shoulder (M1 a-Mn) can be, and [su carrying on shoulder (M1 a-Mn) electrodes are common column line (C) of number 2 through common post - is faster circuit (20) can be electrically connected. The idea is to 5 and also to understand the reference in the embodiment 10 may be also are disclosed. Figure 12 shows a of the present invention also one in the embodiment according to pattern recognition system (900) in general outline a timing block diagram illustrating this disclosed. E.g., said pattern recognition system (900) a voice recognition system (speech recognition system), Image recognition system (imaging recognition system), code recognition system (code recognition system), signal recognition system (signal recognition system), or a variety of other patterns for recognizing one of the system can be. The reference also 12, one of the present invention in the embodiment according to pattern recognition system (900) includes a central processing unit (910), memory unit (920), the unit communication number (930), network (940), output unit (950), input unit (960), analog - digital converter (970), neuro morphics associated therewith unit (980), and/or bus (990) can be a. A central processing unit (910) is neuro morphics associated therewith unit (980) produces and transmits signals and various learning, and neurotrophin morphics associated therewith unit (980) output from the voice, such as pattern recognition of Image can be performing various processing and function. Said central processing unit (910) memory unit (920), the unit communication number (930), output unit (950), analog - digital converter (970) and neurotrophin morphics associated therewith unit (980) a bus (990) can be connected via. Memory unit (920) the pattern recognition system (900) can be stored at various information required. Memory unit (920) (DRAM) dram or SRAM (SRAM) such as volatile memory device, (PRAM), MRAM (MRAM), egg ram (ReRAM), or non-volatile memory such as a NAND flash memory (NAND flash memory), or hard disk drive (HDD) or solid state drive (SSD) comprising at least one of various storage unit can be. The unit communication number (930) recognizing voice, Image data such as a network (940) number through the unit or otherwise and/or receiving communication of different systems can be. Output unit (950) recognizing voice, data such as Image can be output in a variety of ways. For example, output unit (950) speaker, printer, monitor, display panel, beam projector, holographic fixed, or output device can be a variety of other types. Input unit (960) microphone, camera, scanner, touch pad, keyboard, mouse, mouse pen, or a variety of sensors comprising at least one can. Analog - digital converter (970) input device (960) can be converted from analog data into digital data. Neuro morphics associated therewith unit (980) analog - digital converter (970) stores data output from (learning), recognition (recognition) can perform, data corresponding to the fingerprint pattern can be output. Neuro morphics associated therewith unit (980) the technical idea of the present invention may be provided with a neurotrophin morphics associated therewith at least one of various elements in the embodiment can. Or more, for example with reference to the attached drawing of the present invention embodiment described but, in the present invention is provided to the present invention is technical idea or person with skill in the art without changing its essential features can be understand other specific embodiment can form are disclosed. The exemplary embodiment described above are not limited to examples in all of which must not understood to 2000. 10, 1 10 _ provided _n 10: pre - is faster circuit 20: Post - is faster circuit 30, 30A - 30n: synapse SC1 provided SCn: synaptic cell T1 provided Tn: transistor M1 a-Mn: [su carrying on shoulder R, R1 a-Rn: the row lines C: column line The present invention provides a neuromorphic device including a synapse having multiple synapse cells. The neuromorphic device comprises: a pre-synaptic circuit; a post-synaptic circuit; and a synapse electrically connected to the pre-synaptic circuit and the post-synaptic circuit. The synapse includes the multiple synapse cells which are connected to the pre-synaptic circuit through each of multiple row lines and electrically connected to the post-synaptic circuit through a common column line. COPYRIGHT KIPO 2018 Pre - is faster circuit; post - is faster circuit; and said pre - and post - is faster circuit and said synapse is faster circuit electrically connected, via said plurality of row lines is faster pre - said synapse each is connected to a common column line through said post - and is faster circuit electrically connected to the plurality of synaptic cells including neuro morphics associated therewith element. According to Claim 1, said plurality of synaptic cells each include at least one transistor and at least one including neuro morphics associated therewith element. According to Claim 2, said one synapse included in said plurality of synaptic cells transistors are different current driving efficiency having neuro morphics associated therewith element. According to Claim 2, said transistors are, each, said plurality of row lines electrically connected products are morphics associated therewith element. According to Claim 4, the drain electrodes of said transistors, respectively, and electrically connected to said plurality of row lines, and said pixel electrodes are, each, said products are electrically connected to corresponding morphics associated therewith element. According to Claim 4, said plurality of said row lines and said transistors each and electrically connected with the drain electrodes, and said common column line and electrically connected to said pixel electrodes are the neurotrophin morphics associated therewith element. According to Claim 4, said transistor gate electrodes, respectively, and electrically connected to said plurality of row lines, and said transistors drain electrodes are, respectively, electrically connected to the reference voltage node products are morphics associated therewith element. According to Claim 2, said plurality of synaptic cells, each, different numbers of transistors including neuro morphics associated therewith element. According to Claim 8, said transistors in parallel with each other said same synaptic cell connected neuro morphics associated therewith element. According to Claim 9, said same synaptic cell that the gates of said common electrodes are electrically connected neuro morphics associated therewith element. According to Claim 8, said that the gates of the electrodes are, each, said synapse cell products are commonly connected row lines connected said morphics associated therewith element. According to Claim 11, said transistors drain electrodes electrically connected to a reference voltage node products are morphics associated therewith element. According to Claim 1, said plurality of synaptic cells, each, transistor and and, said each synapse cells [su carrying on shoulder use different said fixed resistor element with values in neuro morphics associated therewith. Pre - is faster circuit; post - is faster circuit; and said pre - and post - is faster circuit and said synapse is faster and electrically connected to the circuit, said plurality of synaptic cells including neuro morphics associated therewith different current driving efficiency for their use in the element. According to Claim 14, said plurality of synaptic cells, each, transistor and and, said different channel sized neuro morphics associated therewith each synapse cell said each transistor element. According to Claim 14, said plurality of synaptic cells, each, different numbers of transistors and one including neuro morphics associated therewith element. According to Claim 14, said plurality of synaptic cells, each, transistor and and, said each said fixed resistance value neuro morphics associated therewith different each synapse cell element. According to Claim 14, said plurality of synaptic cells are a plurality of row lines independently from other said pre - and electrically connected to the circuit and is faster, and common column line through said post and electrically connected to the circuit is faster for the neurotrophin - commonly morphics associated therewith. Current levels T1 T2 Channel size 0 Off Off 0 1 On Off W 2 Off On 2W 3 On On 3W Current levels T1 T2 T3 Channel size 4 Off Off On 4W 5 On Off On 5W 6 Off On On 6W 7 On On On 7W Current levels T1 (1W) T2 (2W) T3 (4W) T4 (8W) Channel size 8 Off Off Off On 8W 9 On Off Off On 9W 10 Off On Off On 10W 11 On On Off On 11W 12 Off Off On On 12W 13 On Off On On 13W 14 Off On On On 14W 15 On On On On 15W
