SEMICONDUCTOR DEVICE
The present invention refers to semiconductor device relates to, formed with the improved semiconductor device provided a number [...] 30 to 60 seconds. Size, board and/or low number tank costs due to characteristics of semiconductor device conductive element to penetrate through the electronics industry etc. is important. However, highly developed by the electronics industry, high integration of semiconductor tends etc. are selectively grown. For high integration of semiconductor, etc. is becoming reduced line width of pattern of semiconductor. However, recently patterns such as micronized and/or high-cost exposure technology requires new exposure technology is applied, etc. semiconductor nitride layer is becoming difficult. The, recently, new integrated circuits are described forward more for progressing disclosed. The present invention formed with the improved semiconductor device if a number [...] number notifies the and 30 to 60 seconds. The present invention is the number to one or more pipeline and number and number if not, another and number are not mentioned below may be clearly understand one skilled from the substrate are disclosed. According to an embodiment of the present invention includes a semiconductor device substrate including active region number 1 which extends in a direction, said active region overhangs transforming said number 1 number 2 bit line structures, said bit line structure on a substrate disposed on said one side wall of said bit line structures between said adjacent spacer and number 1 disposed on the end of an active region comprising a storage node contact, said number 1 number 1 bit line structures with each said storage node contact between said spacer portion, said portion between said number 1 number 2 portion and said number 1 number 3 portion between the storage node contact portion comprising said number 2, said number 1 portion of minimum vertical thickness greater than said number 3 maximum vertical thickness, maximum vertical thickness of said number 3 maximum vertical can be greater than the thickness of said number 2. Said number 1 can be surrounded by said insulating spacer insulating film and air gap. Insulating layer is used as said number 1 portion is number 1, number 2 insulating layer is used as said number 2 portion, and said number 3 portion is surrounded by a insulating film comprising said number 3 number 3 insulating air gap, said number 1 insulating film, said number 2 insulating film and said number 3 insulation layer can be the same material. Said number 3 portion of minimum vertical thickness equal to said number 2 can be maximum vertical thickness. An upper surface of the edge portion by means of which the number 1 portion and said number 2 exposed said number 3, said edge can be angled. An upper surface of the edge portion by means of which the number 1 portion and said number 2 exposed said number 3, said edge be rounded. Said bit line structure disposed on the other side of the sidewall, said outer tube extend, said number 1 number 2 opposite spacer further comprising a spacer, said number 2 spacer, said bit line structures with each storage node contact between said portion and said number 1 number 1 number 2 portion between storage node contact portion comprising, said number 1 portion of minimum vertical thickness can be greater than the thickness vertical maximum said number 2. Maximum vertical thickness equal to said thickness of said number 1 can be of minimum vertical said number 1. Maximum vertical thickness of said minimum vertical thickness of said number 2 can be equal to said number 2. An upper surface of the portion said number 2 can be located at a higher level than the upper surface drain. According to an embodiment of the present invention, number 1 number 2 formed between the sacrificial spacer sub spacer sub spacer etch process for forming landing pads exposed, a stand-alone number to selectively exposed sacrificial spacer, said spacer having an air gap there between storage node contact bit line can be. The, landing pad while ensuring a minimum threshold width, can be provided to reduce parasitic capacitance between storage node contact bit line. Figure 1 shows a semiconductor device of the present invention in the embodiment according to indicating the plane are also are disclosed. The semiconductor device according to an embodiment of the present invention also 2a in the chemical formula, of Figure 1 I a-I 'ray and II a-II' 16 cross-sectional drawing line directions are disclosed. For the enlargement portion 2a and 2b is also enlarged inclusion of A also also 2c also. According to an embodiment of the present invention also includes a semiconductor device 3a in the chemical formula, of Figure 1 I a-I 'ray and II a-II' 16 cross-sectional drawing line directions are disclosed. 3a and 3b 3c is also enlarged for the enlargement of portion B also may also work environment. According to semiconductor device of the present invention in the embodiment are plane view indicating number of bath method is also 4a to 18a are disclosed. The semiconductor device according to an embodiment of the present invention also includes a method of revealing the secret number tank 18b also to 4b, also 4a to 18a of I a-I 'ray and II a-II' 16 cross-sectional drawing line directions are disclosed. Figure 27 shows a method of semiconductor device according to an embodiment of the present invention revealing the secret number is also also 19 to tank, also 4a to 18a of I a-I 'ray and II a-II' line directions cross-section 16 are disclosed. Advantages and features of the present invention, achieve the appended drawing method and an electronic component connected to the reference surface with specifically carry activitycopyright will in the embodiment. In the present invention refers to hereinafter however limited to the disclosure in the embodiment but can be embodied in the form of various different, in the embodiment of the present invention disclosure is to only the completely, to complete the present invention of the invention is provided to a target number for informing a person with skill in the art categories in which ball, defined by category of the present invention refers to claim only disclosed. The same references refer to the same components across special specification. The specification describes in the embodiment for the present invention the term used in which relayed a number that is even endured. In the specification, a plurality type comprises a unit in a single may be phrase will not specially mentioned. Used in specification 'includes (comprises)' and/or 'including (comprising)' handle components, steps, operation and/or element comprises at least one other components, steps, operation and/or devices does not number the presence or addition times. In addition, in the embodiment of the present invention are discussed specification the ideal example products on be described and/or plane view that excels in the cross-sectional drawing are disclosed. Substrate in drawing, description and technical content of effective for exaggerated thickness regions are disclosed. The, number bath techniques and/or tolerances of form can be modified by example degrees. Thus, the specific number of the present invention in the embodiment shown are but one type of change including process for preparing produced in accordance number are disclosed. For example, the etching area shown at right angles having an predetermined angular or round may be in the form disclosed. The, drawing exemplified regions are coarse has attribute, for example the shape for drawing exemplified areas in the region of the invention which form relayed number categories for endured. Figure 1 shows a semiconductor device of the present invention in the embodiment according to indicating the plane are also are disclosed. The semiconductor device according to an embodiment of the present invention also 2a in the chemical formula, of Figure 1 I a-I 'ray and II a-II' 16 cross-sectional drawing line directions are disclosed. For the enlargement is also enlarged portion of Figure 1 A 2b 2c also and also a low oxide inclusion content. According to an embodiment of the present invention also includes a semiconductor device 3a in the chemical formula, of Figure 1 I a-I 'ray and II a-II' 16 cross-sectional drawing line directions are disclosed. 3a and 3b 3c is also enlarged for the enlargement of portion B also may also work environment. Also 1, 2a and 3a also also reference the, substrate (100) in isolation (111) can be disposed. Substrate (100) bulk (bulk) silicon substrate, silicon - on - insulator (silicon on insulator: SOI) substrate, germanium substrate, germanium - on - insulator (germanium on insulator: GOI) substrate, silicon - germanium substrate, or selective epitaxial growth (selective epitaxial growth: SEG) forming polysilicon layer of the obtained perform may be the substrate disclosed. Isolation layer (111) comprising the insulating material (e.g., silicon oxide) can be. Isolation layer (111) substrate (100) of active areas (AR) can be defining. The elongated bar (bar) (Z) direction (AR) number 3 active regions may have the form. Active regions can (AR) are parallel to each other. Substrate (100) of active areas (AR) within each source drain region (50) can be disposed. Source drain regions (50) substrate (100) having an opposite conductivity type (e.g., N type) may have a. Substrate (100) of active areas (AR) within each pair of word lines (WL) can be disposed. Word lines (WL) (X) (Z) intersecting the direction the number 3 number 1 direction across active region (AR) can be. Word lines (WL) substrate (100) (AR) active region can be embedded in the. I.e., the upper surface of the substrate are word lines (WL) (100) low level than the upper surface of can be located. Word lines (WL) and made of materials which can, for example, polysilicon, doped polysilicon, metal materials, or metal silicide material can be. Word lines (WL) each sidewall and said substrate (100) between and word line (WL) lower surface and the substrate (100) between the select gate (151) can be disposed. A gate insulating film (151) for example, can be silicon oxide or thermal oxide layer. Word line (WL) the top surface of the substrate (100) between the upper surface of the capping pattern (191) can be disposed. The capping pattern (191) the top surface of the substrate (100) located on the same level as the top surface of the can. The capping pattern (191) word line (WL) the lower surface of the upper surface of the gate electrode (151) can be contacted with a sidewall of. The capping pattern (191) comprising the insulating material (e.g., silicon oxide) can be. Substrate (100) on the top surface of buffer layer (70) can be disposed. Buffer (70) includes one or more 110b can be. For example, buffer layer (70) is silicon oxide, silicon nitride or silicon oxide nitride including two or more of the plurality of 110b can be. A pair of word lines (WL) positioned between the substrate (100) (AR) active region (DCC) can be disposed in at least part of a bit line node contact. The bit line node contact (DCC) buffer (70) penetrate, substrate (100) disposed within a portion of source/drain regions (AR) active region (50) can be electrically connected. Bit line node contact (DCC) may be positioned at a higher level than the upper surface of the lower surface of the word line (WL) and, the top surface of the bit line node contact (DCC) buffer (70) may have an upper surface of 151m. For example bit line node contact (DCC), metal silicide, poly silicide, metal nitride, metal layer can be selected from the group including at least one membrane. Substrate (100) direction (X) (AR) active region number 1 and number 2 and number 3 (Z) direction (Y) transverse direction intersecting the bit line structure (BLS) can be arranged. (BLS) bit line structure is arranged in a direction (Y) number 2 (DCC) can be a plurality of bit line node contacts at this time. In one example, bit line structure (BLS) number 2 is arranged in a direction (Y) a plurality of bit line node contacts (DCC) can be electrically connected. (BLS) bit line structure of the substrate (100) are sequentially stacked on bit line (BL) and insulation pattern (240) can be comprising. The bit line conductive pattern number 1 (BL) (232) and conductive pattern number 2 (234) can be comprising. Conductive pattern number 2 (234) is conductive pattern number 1 (232) and insulation pattern (240) can be disposed between. Conductive pattern number 1 (232) for example, can be a polysilicon or doped polysilicon. Conductive pattern number 2 (234) for example, tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), and cobalt (Co) includes either a can. Insulation pattern (240) for example, can be silicon oxide layer. Not shown on the drawing but, conductive pattern number 1 (232) and conductive pattern number 2 (234) (not shown) can be disposed between the diffusion barrier film. (BLS) adjacent bit line structures positioned between the substrate (100) end of the storage node contact (BC) (AR) active region can be arranged. Storage node contact (BC) substrate (100) disposed within the ends of the active region (AR) source/drain regions (50) can be electrically connected. In one example, a plurality of storage node contacts is arranged in a direction (Y) number 2 (BC) can be arrayed in series. Storage node contact (BC) the lower portion of the substrate (100) active region (100) can be embedded in the. The top surface of the insulating pattern storage node contact (BC) (240) low level than the upper surface of can be located. For example storage node contact (BC), metal silicide layer, polysilicon layer, metal nitride and metal film can be at least one. Also 2b, 2c also, 3b and 3c also also possible to reference the, number 1 and number 2 (BLS) bit line structures can be arranged on each side wall spacers (S1, S2). Specifically, one side of the bit line structure (BLS) and spacer (S1) can be positioned on the wall of number 1, number 2 (S2) of (BLS) bit line structure can be disposed on other side wall spacer. In one example, spacer (S1) and (S2) number 1 number 2 is an outer spacer can be opposing each other in the storage node electrode (BC). Number 1 spacer (S1) (S2) (BC) spacer upper and number 2 can be exposed by the top of the storage node contact. Number 1 (S1) and (S2) spacer for specific description is to carry spacer number 2 to each other. Buffer (70) disposed on, and having plural adjacent bit line structures (BLS) (WL) area between the part of the separation pattern (272) can be disposed. Separation pattern (272) for example, SiBCN film, SiCN film, SiOCN film, and it includes at least one SiN film can. Storage node contact (BC) (LP) can be disposed on landing pad. Landing pad (LP) (BC) can be electrically connected with the storage node contact. A portion of the bit line structures (BLS) (LP) landing pad adjacent to each other can be disposed on either. In one example, landing pad upper surface of the separation pattern (LP) (272) located on the same level as the top surface of the can. (LP) is landing pad is made of substrate having the storage node electrode (BC) (252) and metal pattern (254) can be comprising. Substrate having (252) the metal pattern (254) (BC) storage node contact between, metal pattern (254) and spacer (S1) between an upper portion of number 1 and metal pattern (254) and insulation pattern (240) between the upper surface of the, and metal pattern (254) and spacer (S2) can be interposed between an upper portion of number 2. Substrate having (252) for example, TiN, Ti/TiN, TiSiN, comprising TaN or WN can be. Metal pattern (254) comprising metal material (e.g., tungsten) can be. (LP) layer between adjacent landing pads (276) can be disposed. Layer (276) (LP) can be wall encloses the landing pads. Layer (276) the lower surface of the insulating pattern (240) the top surface of the insulating pattern (240) can be disposed between the lower. In one example, layer (276) spacer (S2) an insulation pattern adjacent a portion of the number 2 (240) can be embedded in the. Layer (276) part number 2 (S2) can be in contact with the lower surface of spacer. Layer (276) may have an upper surface of the top surface of the landing pad 151m (LP). Layer (276) insulating the number 1 (276a) and number 2 insulating film (276b) can be comprising. Number 1 insulating film (276a) (L) are adjacent landing pads wall, insulation pattern (240) can be in contact with a portion of the sidewall and spacer number 2 (S2). Number 1 insulating film (276a) the step coverage (step a-coverage) can do not agree with each insulating material. Number 1 insulating film (276a) for example, TEOS (tetraethly orthosilicate) or high density plasma (HDP) oxide layer can be. Number 2 insulating film (276b) insulating the number 1 (276a) can be the interior space. Number 2 insulating film (276b) for example, can be silicon oxide film or the silicon nitride. (LP) landing pad information on storage elements can be arranged. Data storage elements can be e.g. capacitor. Capacitor lower electrode (BE), dielectric layer (not shown) and an upper electrode (not shown) can be include. In one example, the lower electrodes (BE) scan direction (Y) number 2 can be. In to, also 2b, 2c also, and also with reference to the 3b 3c also, spacer (S1) and (S2) number 1 number 2 spacer for specifically illustrating the substrate. The reference also and also 2b 3b, number 1 (S1) (BSL) bit line structure includes a spacer with a portion of storage node contact (BC) and between bit line structure (BSL) (LP) number 1 (P1) disposed between other portions of the landing pad portion, part number 1 (P1) (P1) (BC) as the portion of the storage node contact portion between number 1 and number 2 (P2) disposed between other portions of the landing pad portion (LP), number 1 and number 2 and number 3 (P3) (P1) (P2) between a portion portion portion can be. In one example, part number 1 (P1) (P3) (t1) minimum vertical thickness is number 3 (T3) and be larger than the maximum vertical thickness portion, part number 3 (P3) (P2) (T3) is maximum vertical thickness can be greater than maximum vertical thickness (T2) part number 2. Part number 3 (P3) (P2) (t3) number 2 is minimum vertical thickness portion (T2) can be substantially the same maximum vertical thickness on. The insulating layer is used as part number 1 number 1 (P1), (P2) insulating layer is used as the part number 2 number 2, number 3 (P3) is part number 3 number 3 (AG) can be surrounded by insulating air gap comprising an insulating film is formed. The upper surface of number 1 (P1) portion (2a) portion upper surface of the number 2 (P2) (2b) located at a higher level than, number 3 upper surface of portion (P3) (2c) number 1 (P1) the upper surface of portion (2a) and the upper surface of part number 2 (P2) (2b) level can be located. In one example, the upper surface of the insulating air gap defined number 3 (AG) (2d) number 1 (P1) the upper surface of portion (2a) and the upper surface of part number 2 (P2) (2b) level can be located. The upper surface of part number 2 (P2) (2b) located at a higher level than the upper surface of the storage node contact (BC) can be. The upper surface of number 1 (P1) portion (2a), the upper surface of number 2 (P2) portion (2b) and the upper surface of number 3 (P3) portion (2c) can be contact landing pad (LP). The upper surface of part number 3 (P3) (2c) portion (P1) the number 1 and number 2 (P2) can be exposed by the portion. In one example, such as also shown in 2b, number 3 upper surface of portion (P3) (2c) (P3) to the top of the corner portion and including number 3, the corners be rounded. As another alternative, such as also shown in 3b, part number 3 (P3) and the top of the corner, the corners can be angled. Spacer number 2 (S2) (BC) (BSL) bit line structure with a portion of the storage node contact between each other and other portions of the bit line structure (BSL) (LP) landing pad disposed between part number 1 (P1 '), part number 1 (P1') (BC) number 1 (P1 ') as the portion of the storage node contact between each other and other portions of the landing pad portion (LP) can be disposed between a part number 2 (P2'). In one example, part number 1 (P1 ') minimum vertical thickness is greater than the maximum vertical thickness (T2') part number 2 (P2 ') (t1') can be. And, part number 1 (P1 ') (T1') number 1 (P1 ') maximum vertical thickness is substantially the same minimum thickness on vertical portion (t1') can be, part number 2 (P2 ') (T2') number 2 (P2 ') maximum vertical thickness portion has substantially the same thickness on vertical minimum (t2') can be. Also 2c and 3c also reference the, number 1 (S1) is sub spacer (SP1) spacer number 1, number 2 (SP2) sub spacer, spacer (SP3) sub number 3, and air gap comprising (AG) can be. A bit line (BL) number 1 (SP1) (BC) and between the storage node contact sub spacer insulating pattern (240) can be disposed between a portion of a landing pad with a portion of (LP). Sub spacer (SP1) is number 1 buffer (70) number 1 (CH1) the substrate exposed portions of the top and/or contact hole (100) extending on the top surface of can be. In one example, sub-spacer (SP1) bit line (BL) is one side wall of a portion of number 1, insulation pattern (240) one side wall of, substrate having (252) and a portion of the buffer layer (70) can be contacted with a sidewall of. In one example, sub-spacer (SP1) bit line (BL) is one side wall of a portion of number 1, insulation pattern (240) one side wall of, substrate having (252) contact hole number 1 (CH1) and a portion of the substrate exposed (100) can be contacted with a sidewall of. (SP1) is further provided spacer sub number 1 for example, can be a silicon nitride. Number 2 number 1 (SP1) (SP2) sub spacer with a portion of storage node contact (BC) sub spacer is positioned between a portion of and other portions of the storage node contact (BC) number 1 (SP1) sub spacer adjacent (LP) can be disposed between a portion of a landing pad. In one example, number 2 (SP2) (BC) storage node electrode is sub spacer portion (LP) can be landing pad sidewall of the portion. In one example, the upper surface of spacer sub number 2 (SP2) (2b) upper surface of the spacer (SP1) sub number 1 (2a) can be located lower-level. (SP2) is further provided spacer sub number 2 for example, can be a silicon nitride. Number 1 and number 2 is number 3 (SP3) spacer (SP1) sub sub spacer upper sidewall of the upper surface of spacer (SP2) sub (2b) can be disposed between. In one example, the spacer (SP1) number 3 (SP3) upper sidewall of spacer sub sub number 1, number 2 (SP2) sub spacer upper surface of (2b) perpendicular to the first and the portion (LP) can be landing pad. A bit line node contact (BC) of number 3 (SP3) sub spacer can be disposed on the top surface. I.e., number 3 (SP3) sub spacer can be exposed by a bit line node contact (BC). The thickness of the spacer sub number 3 (SP3) (SP2) thereof can thickness less than that of spacer sub number 2. Sub spacer (SP3) number 3 for example, can be a silicon nitride. A bit line (BL) air gap (AG) (BC) and between the insulation pattern storage node contact (240) (LP) as the portion of the landing pad can be disposed between. The air gap spacer (SP1) (AG) sub number 1, number 2 (SP2) sub spacer, number 3 and number 1 and number 2 (SP2) spacer (SP1) sub spacer (SP3) sub sub spacer exposed by the storage node electrode (BC) corresponding to part of a vessel can be surrounded. In one example, the upper surface of air gap defined by a spacer sub number 3 (SP3) (AG) (2d) upper surface of the spacer (SP1) sub number 1 (2a) and the upper surface of spacer sub number 2 (SP2) (2b) level can be located. (S2) is sub spacer (SP1 ') spacer number 2 number 1, number 2 sub-spacer (SP2'), number 3 (SP3 ') and air gap (AG') can be sub-spacer comprising. Storage node contact (BC) number 1 (SP1 ') bit line (BL) is sub spacer between each other and insulation pattern (240) (LP) as the portion of the landing pad can be disposed between. Number 1 is sub spacer (SP1 ') buffer (70) number 1 (CH1) the substrate exposed portions of the top and/or channel hole (100) extending on the top surface of can be. In one example, sub bit line (BL) other sidewall spacer (SP1 ') is number 1, insulation pattern (240) portion of the other sidewall, number 1 insulating film (276a) buffer the lower surface of a portion (70) can be contacted with a sidewall of. In one example, sub bit line (BL) other sidewall spacer (SP1 ') is number 1, insulation pattern (240) portion of the side wall of the other side of the, number 1 insulating film (276a) number 1 (CH1) and the lower surface of the substrate exposed portion channel hole (100) can be contacted with a sidewall of. Number 1 sub spacer (SP1 ') is further provided for example, can be a silicon nitride. As the portion of the storage node contact spacer (SP1 ') number 1 number 2 (SP2') sub sub spacer is positioned between a portion of and number 1 (BC) sub spacer (SP1 ') to other portions of the storage node contact (BC) (LP) can be disposed between a portion of a contiguous with landing pad. In one example, number 2 (BC) landing pad portion sidewall of storage node electrode is sub spacer (SP2 ') the portion (LP) can be. In one example, the upper surface of a top surface of the spacer (SP1 ') sub number 1 number 2 sub-spacer (SP2') can low level position. (SP2 ') is further provided spacer sub number 2 for example, can be a silicon nitride. The top of the insulating spacer (SP2 ') number 2 is number 3 (SP3') sub spacer sub number 1 (276a) can be disposed between the lower surface of part. In one example, the upper surface of spacer sub number 3 (SP3 ') is number 2 (SP2') sub-spacer portion, and a portion of the landing pad (LP) number 1 insulating film (276a) can be in contact with the bottom surface of. (SP3 ') is further provided spacer sub number 3 for example, can be a silicon nitride. A bit line (BL) air gap (AG ') (BC) and between the insulation pattern storage node contact (240) can be disposed between a portion of a landing pad with a portion of (LP). The air gap spacer (SP1 ') (AG') sub number 1, number 2 sub-spacer (SP2 '), spacer sub number 3 (SP3'), number 1 insulating film (276a) and spacer (SP1 ') portion of sub number 1 and number 2 sub-spacer (SP2') (BC) exposed by the storage node electrode is part of a corresponding free space can be surrounded. The upper surface of spacer (SP1) on the uppermost surface (S1) number 1 spacer sub number 1 (2a) can be defined. The upper surface of the uppermost surface sub number 1 number 2 (S2) spacer (SP1 ') spacer (2a'), the upper surface of spacer sub number 3 (SP3 ') (2c') and defining insulating air gap (AG ') number 1 (276a) can be defined by a lower surface part. The, number 1 (S1) (S2) on the uppermost surface of the uppermost surface spacer spacer number 2 can be located at different levels. In one example, spacer (S1) (S2) on the uppermost surface number 1 number 2 can be located at a higher level than the top surface of the spacer According to semiconductor device of the present invention in the embodiment are plane view indicating number of bath method is also 4a to 18a are disclosed. The semiconductor device according to an embodiment of the present invention also includes a method of revealing the secret number tank 18b also to 4b, also 4a to 18a of I a-I 'ray and II a-II' 16 cross-sectional drawing line directions are disclosed. Also 4a and 4b also reference the, substrate (100) in isolation (111) defining active regions (AR) can be formed. Isolation layer (111) substrate (100) (not shown) to form trenches, can be formed within trenches filled with insulating material. The elongated bar (bar) to number 3 (Z) direction (AR) active regions has a form which, can be disposed parallel to one another. Substrate (100) bulk (bulk) silicon substrate, silicon - on - insulator (silicon on insulator: SOI) substrate, germanium substrate, germanium - on - insulator (germanium on insulator: GOI) substrate, silicon - germanium substrate, or selective epitaxial growth (selective epitaxial growth: SEG) forming polysilicon layer of the obtained perform may be the substrate disclosed. Isolation layer (111) for example silicon oxide, silicon oxynitride or a silicon nitride may include disclosed. The 5a and 5b also reference also, source/drain regions within each active regions (AR) (50) can be formed. Source/drain regions (50) substrate (100) (not shown) is formed on an ion implantation mask, the substrate exposed ion implantation mask (100) can be conductive pattern is exposed in an ion implantation process. Alternatively, ion implantation is made without ion implantation mask can be. Substrate (100) in trenches (131) can be formed. A pair of trenches (131) (Z) intersecting the number 1 to number 3 (AR) active area are formed transverse direction (X) direction can be. Trenches (131) are parallel to each other can be arranged. Trenches (131) each surface to be [khen foam metal lines (151) can be formed. A gate insulating film (151) is made of an insulating material and, for example, silicon oxide film or thermal oxidizer main disclosed. A gate insulating film (151) surrounded by a trench (131) in the word line (WL) can be formed. (WL) word line gate insulating (151) on a (131) metal film (not shown) is formed filling, trench (131) etched in a lower part of metal to be remained metal film can be formed. Word line (WL) and made of materials which can, for example, polysilicon or doped polysilicon, metal materials, or metal silicide material can be. Trench (131) into the intermediate space the remainder of the capping pattern (191) can be formed. The capping pattern (191) (WL) word lines formed on, trench (131) can be fully filled. The capping pattern (191) for example, silicon oxide, silicon oxynitride or a silicon nitride may include disclosed. Also 6a and 6b also reference the, substrate (100) on the buffer oxide film (70) can be formed. Buffer (70) comprises at least one insulating layer can be composed. Buffer (70) for example, silicon oxide, silicon nitride, silicon oxynitride or two or more thereof including a plurality of insulating film than the disclosed. Shown in the drawing but, buffer (70) (not shown) openings (not shown) on a mask having a pattern can be formed. Exposed mask pattern buffer (70) for patterning the barrier metal layer can be performed. Etching the buffer layer (70) and a portion of substrate (100) is etched to the upper portion, (AR) active region can be formed in the contact hole number 1 (CH1). Specifically, in terms of flat, contact hole number 1 (CH1) (AR) active region overlap with the source/drain region disposed between the pair of word lines (WL) (50) can be exposed. Number 1 while forming a contact hole (CH1), source/drain regions (50) adjacent isolation layer (111) be etched in the upper portion. The reference also 7a and 7b also, contact hole number 1 (CH1) in contact pattern (215) can be formed. Contact pattern (215) number 1 (CH1) for complete filling of the contact hole can be formed. Specifically, contact pattern (215) buffer film (70) number 1 (CH1) (not shown) is formed on channel hole filling conductive film, buffer (70) until the upper portion of dielectric layer (e.g., etch back or CMP) planarization process can be the conductive pattern is exposed. Contact pattern (215) metal silicide, poly silicide, metal nitride, metal layer can be selected from the group including at least one membrane. The 8a and 8b also reference also, buffer layer (70) on the electrode membrane (230) can be formed. Electrode film (230) comprising a plurality of conductive films can be. For example, electrode film (230) buffer film (70) number 1 are sequentially stacked on the electrode membrane (231) and number 2 electrode film (233) can be comprising. Number 1 electrode film (231) for example, can be a polysilicon or doped polysilicon. Number 2 electrode film (233) for example, tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), or cobalt (Co) can be a. But shown in the drawing, number 1 electrode film (231) and number 2 electrode film (233) (not shown) can be interposed between the diffusion barrier film. Thermal process is performed as barrier metal (diffusion barrier metal), e.g. TiN, Ti/TiN, TiSiN, comprising TaN or WN can be. Electrode film (230) on the insulating pattern (240) can be formed. A plurality of insulating patterns (240) number 2 is substantially extends in the direction (Y), can be arranged parallel to each other. Insulating patterns (240) each contact patterns arranged in a direction (Y) number 2 (215) to on (AR) can be across through the active regions. Insulation pattern (240) can be silicon oxide or silicon nitride. Also 9a and 9b also reference the, insulation pattern (240) is etched using, insulation pattern (240) exposed electrode film (230) is patterned to form a bit line (BL) can be formed. Then, contact pattern (215) by performing an etching process, contact hole (CH1) number 1 in bit line node contact (DCC) can be formed. Bit line (BL) on bit line node contact (DCC) to a direction (Y) transverse number 2 through the active region (AR) can be. Bit line (BL) and method of bit line node contact (DCC) is formed, buffer (70) contact hole (CH1) portion of the top surface and number 1 (AR) active region in the semiconductor film is (111) can be exposed. Bit line (BL) substrate (100) are sequentially stacked conductive pattern on number 1 (232), conductive pattern number 2 (234) can be comprising. The 10a and 10b also reference also, conductive pattern number 1 (232) sidewalls, conductive pattern number 2 (234) sidewalls, insulation pattern (240) sidewalls and an upper side, buffer (70) the upper surface of the, bit line node contact (DCC) number 1 (CH1) and sidewalls of the contact hole surface of spacer [khen foam coverage is number 1 (301) can be formed. Spacer number 1 (301) for example, can be a silicon nitride. Spacer number 1 (301) sacrificial spacer (303) can be formed. Sacrificial spacer (303) is spacer number 1 (301) to be [khen foam surface of thereof can cover. In one example, sacrificial spacer (303) a bit line node contact (DCC) number 1 (CH1) not the remaining area of the contact hole is filled with the filling disclosed. Sacrificial spacer (303) is number 1 spacer (303) and having etch selectivity can be material. For example, sacrificial spacer (303) can be silicon oxide layer. Sacrificial spacer (303) number 2 on spacer (305) can be formed. Spacer number 2 (305) sacrificial spacer (303) [khen foam surface of part thereof can cover. Spacer number 2 (305) sacrificial spacer (303) and having etch selectivity can be material. For example, spacer number 2 (305) can be silicon nitride. The 11a and 11b also also reference, an etch-back process is performed, insulation pattern (240) and the upper surface of the buffer layer (70) to the upper portion of spacer number 2 (305), sacrificial spacer (303) and spacer number 1 (301) are sequentially etching can be disclosed. The, conductive pattern number 1 (232), conductive pattern number 2 (234), insulation pattern (240) and spacer formed on sidewalls of the bit line node contact (DCC) are sequentially stacked sub number 1 (SP1), sacrificial spacer (303a) and number 2 sub-spacer (SP2) can be formed. Buffer (70) on the oxide layer is formed between bit lines (BL) (310) can be formed. Insulating film (310) the top surface of the insulating pattern (240) may have an upper surface of 151m. Insulating film (310) for example, silicon oxide, silicon nitride, or silicon oxide nitride layer including a plurality of insulating film than the disclosed. The reference also 12a and 12b also, insulating film (310) can be formed by openings (OP) as an etch mask. In terms flat, each space between adjacent bit lines (BL) openings (OP) and having plural area where (BL) can be formed. Openings (OP) filled with insulating material in separation patterns (272) can be formed. Shown in the drawing but, separation patterns (272) are the upper surface of the insulating pattern (240) can be the upper surface of the 151m. Separation patterns (272) insulating film (310) comprising a material having etch selectivity with respect to the can. Separation patterns (272) for example, SiBCN film, SiCN film, and SiN SiOCN film can be at least one. Insulating film (310), insulating film (310) the number of special paper exposed buffer layer (70) and substrate (100) by etching the portion of, number 2 (CH2) contact hole can be formed. Contact hole number 2 (CH2) number 2 (Y) direction and facing each other adjacent bit lines (BL) isolated patterns (272) can be defined by. Number 2 (CH2) contact hole are formed within each of the ends of the active region by (AR)/drain region (50) can be exposed. On the other hand, make the etching process, sacrificial spacer (303a) and spacer (SP2) be etched portions of sub number 2. The 13a and 13b also also reference, number 2 (CH2) contact hole can be formed in the storage node contact (BC). Storage node contact (BC) on the ends (AR) are arranged in the active region, source/drain regions (50) can be electrically connected. A portion of the storage node contact (BC) number 2 (CH2) contact hole filling disclosed. Specifically, number 2 (CH2) film (not shown) fills contact hole formed, conductive etching process (e.g., an etch-back process performed (etch a-back process), lower portion of the storage node contact hole (CH2) channel number 2 (BC) can be formed. The top surface of the insulating pattern storage node contact (BC) (240) can be disposed between upper and lower surfaces of. Storage node contact (BC) by spacer (SP1) portion of sub number 1, sacrificial spacer (303a) of a portion of spacer (SP2) sub number 2 can be etched. For example storage node contact (BC), metal silicide layer, polysilicon layer, metal nitride layer, including at least one membrane layer partially group can be. Storage node contact (BC) exposed by number 2 (SP2) number of sub spacer 1308. volatile portion. The, number 2 (SP2) sub spacer covered by a sacrificial spacer (303a) can be etched sidewall. Number of special process is sacrificial spacer (303a) can be for selectively etching using the photoresist. Number of special process include wet etching or dry etching process can be performed. The reference also 14a and 14b also, number 2 (SP2) exposed by the storage node contact (BC) a sacrificial spacer sub spacer (303a) be etched in the upper portion. The, sacrificial spacer (303a) can be linear slope of the top portion. The, sacrificial spacer (303a) (BC) the top of the storage node contact exposed sacrificial spacer (303a) corresponding to a portion of the can be. Etching of sacrificial spacer (303a) sub number 2 the top of the spacer (SP2) can be exposed by the storage node contact (BC). Sacrificial spacer (303a) number 2 upper sidewall of the contact hole (CH1) can be convex towards. In one example, sacrificial spacer (303a) number 1 (CH1) the top of the channel hole may have a circular protruded toward a side wall. For example etching process, dry etching process (e.g., etch back) can be. The upper surface of the storage node contact (BC), sacrificial spacer (303a) upper sidewall of, sacrificial spacer (303a) spacer (SP1) a sidewall of a portion insulation pattern exposed by the sub number 1 (240) [khen foam coverage is number 3 upper surface of spacer (307) can be formed. Spacer number 3 (307) is number 2 sub-spacer (SP2) can be identical to the material. For example, spacer number 3 (307) can be silicon nitride. The reference also 15a and 15b also, storage node contact (BC) of the top and insulation pattern (240) spacer covering a top face of number 3 (307) number number 3 (SP3) to a portion of a stand-alone sub spacer can be formed. Etching, portions of the top and insulating pattern storage node contact (BC) (240) can be the upper portion of. Number 1 and number 2 (SP1, SP2) number 3 (SP3) includes a spacer sub sub spacers exposed by the sacrificial spacer (303a) side wall portion, sacrificial spacer (303a) exposed by spacer (SP1) number 1 number 2 (SP2) covering a portion of the upper surface and the side walls of sub sub spacer thereof can. The semiconductor, the thickness of the spacer sub number 3 (SP3) spacer number 3 (307) smaller than the thickness of thereof can. Etching process is a dry etching process can be performed. As an etch mask to the top of the storage node contact (BC) can be disclosed. Etching, to expose portions of the top and side wall spacer (SP2) sub number 2 can be. In one example, the top surface of the storage node contact (BC) can be located on the same level as the top surface of the bit line (BL). In one example, the top surface of the storage node contact (BC) sub number 2 (SP2) low level than the upper surface of spacer can be located. Half of the etching process can be performed. Also 16a and 16b also reference surface, storage node contact (BC) (LP) can be formed on the landing pad. Specifically, landing pad (LP) is the upper surface of the storage node electrode (BC), spacer (SP2) of the top and side wall portion sub number 2, number 3 (SP3) sub spacer side wall, portions of the top and insulating pattern spacer (SP1) sub number 1 (240) (not shown) the upper surface of the [khen foam coverage is barrier film made of a metal film (not shown) is formed on the film number 2 channel hole filling (CH2), barrier metal film is selectively etched to can be anti-reflective coating. A space between the plurality of landing pads (LP) number ball 1308. (O). Landing pads (LP) space (O) can be spaced from each other by 2000. Landing pads (each LP (BC) are sequentially formed on a barrier film and metal layer is patterned to form storage node contact barrier pattern (252) and metal pattern (254) can be comprising. Etching, insulation pattern (240) portion of, insulation pattern (240) formed on a side wall of a part of a portion of spacer (SP1) sub number 1, sub number 1 portion of spacer (SP1) formed on the sacrificial spacer (303a) and sacrificial spacer portion of (303a) formed on a portion of number 3 (SP3) number 1308. sub spacer part of the wetting ability. The, sub-spacer (SP1) portion of number 1, sacrificial spacer (303a) number 3 (SP3) (O) of a portion of a portion sub spacer can be exposed by the space. Also 17a and 17b also reference the, space (O) exposed by the sacrificial spacer (303a) can be a stand-alone selectively number. The, sub number 1 (SP1) (SP2) number 1 and number 2 (SP1) on spacer sub spacer between a void space between a spacer sub number 3 (SP3) on sub-spacer (AS) can be formed. Through empty space (AS), inner surface of spacer (SP1) sub number 1, number 2 (SP2) of one side wall of the spacer sub, number 3 (SP3) number 1 and number 2 (SP1) sub spacer portion of sidewall and spacer (SP2) sub sub spacer exposed by the storage node electrode (BC) to expose portions of the can be. Sacrificial spacer (303a) sub spacer (SP1) is number 1, number 2 (SP2) sub spacer, spacer (SP3) and insulation pattern sub number 3 (240) and having etch selectivity with photoresist 1308. number using the wetting ability. Etching process for example, fluoric acid (HF) or LAL can be performed such as etching using a wet etching solution. Also 18a and 18b also reference the, landing pads (LP) number 1 on insulating film (276a) can be formed. Specifically, number 1 insulating film (276a) upper surfaces the landing pads (LP), space (O) exposed by sidewalls of landing pads (LP), space (O) exposed by the insulating pattern (240) sidewall portion of, space (O) number 1 (SP1) exposed by the upper surface of the spacer sub, number 2 (SP3) upper portion of portions of the top and an empty space (AS) sub spacer thereof can. The, sub-spacer (SP1) number 1, number 2 (SP2) sub spacer, spacer (SP3) sub number 3, number 2 and number 3 (SP2, SP3) (BC) sub spacers exposed by the storage node electrode is number 1 and a portion of the insulating film (246a) surrounded by a portion of the air gap (AG ') and spacer (SP1) sub number 1, number 2 (SP2) sub spacer, number 3 (SP3) sub spacer, and number 2 and number 3 (SP2, SP3) (BC) sub spacers exposed by the storage node electrode is surrounded by a portion of the air gap (AG) can be formed. Number 1 insulating film (276a) is the trouble with resultant step coverage (step a-coverage) can be. Number 1 insulating film (276a) for example, TEOS (tetraethly orthosilicate) or high density plasma (HDP) oxide layer can be. Number 1 insulating film (276a) number 2 on insulating film (276b) can be formed. Number 2 insulating film (276b) insulating the number 1 (276a) and cover the surface of, space filling (O) can be. Number 2 insulating film (276b) for example, can be silicon oxide film or the silicon nitride. Number 2 and spacer are formed on top of the existing method sacrificial spacer by etching the spacer sub, thus increasing its width minimum threshold of landing pad. On the other hand, in order to reduce parasitic capacitance between storage node contact bit line, a stand-alone each etching sacrificial spacer number including layer pattern of the substrate. However, sacrificial spacer etching space formed between the bottom surface of the upper landing pads located below, a stand-alone number sacrificial spacer etching through the spaces the tropics. The, minimum threshold width but secure landing pad, on the surface air gaps inside the spacer to, lowering parasitic capacitance exists in the number point at the disclosed. According to one example, sacrificial spacer (303a) for exposing the space (O), sacrificial spacer (303a) number 1 and number 2 (SP2) upper surface of spacer (SP1) sub sub spacer layer is disposed between the upper weight percent. The, landing pad while ensuring a minimum threshold width, can reduce parasitic capacitance between storage node contact bit line spacer having an air gap that can be. The reference 1 and 2a also again also, the upper surface of the landing pads (LP) is removed from the number 1 and number 2 are plastic (276, 276) third can be performed. The, space (O) number 1 and number 2 locally in plastic (276a, 276b) including a layer (276) can be formed. Information on storage elements (e.g., capacitor) landing pads (LP) can be formed. Data storage elements each lower electrode (BE), dielectric layer (not shown) and an upper electrode (not shown) can be include. Figure 27 shows a method of semiconductor device according to an embodiment of the present invention revealing the secret number is also also 19 to tank, also 4a to 18a of I a-I 'ray and II a-II' line directions cross-section 16 are disclosed. For liver deficiency, according to an embodiment of the present invention semiconductor device subjected to the same element of the same drawing number bath described method code is used, redundant description dispensed the on-sensors other. The reference also 19, number 2 (CH2) contact hole can be formed in the storage node contact (BC). A portion of the storage node contact (BC) number 2 (CH2) contact hole filling disclosed. Sub spacer (SP1) number 1, number 2 (SP2) and sacrificial spacer sub spacer (303a) portions of storage node contact (BC) can be exposed by. 20 also reference surface, storage node contact (BC) exposed by number 2 (SP2) number of sub spacer portion can be a stand-alone. Sub spacer (SP2) number 2 covered by a sacrificial spacer (303a) can be etched sidewall. , the sacrificial spacer exposed by the storage node contact (BC) (303a) to increase the surface area of the upper sidewall of can. The upper surface of the upper surface of the storage node contact (BC) number 2 sub-spacer (SP2) can be 151m. Etching the sacrificial spacer (303a) etching recipe (e.g., phosphoric acid) having etch selectivity with respect to using wet etch process can be performed. The reference also 21, exposed by the storage node contact (BC) a sacrificial spacer (303a) portion of number can be a stand-alone. The, sidewall spacer (SP1) sub number 1 can be etched. Sacrificial spacer (303a) (BC) the top surface of the storage node contact an upper surface of spacer (SP2) can be 151m sub portions of the top and number 2. The number 1 and number 2 (SP2) sub spacer (SP1) etching process for sub spacer etching recipe (e.g., fluoric acid or LAL solution) having etch selectivity using wet etch process can be performed. The reference also 22, storage node contact (BC) portion of number can be a stand-alone. The, upper surface of the storage node contact (BC) spacer (SP2) and sacrificial spacer sub number 2 (303a) of lower-level surfaces can be located. Storage node contact (BC) sliding along the volatile portion of number, number 2 (SP2) can be etched sidewalls of the spacer sub. For example etching process, a dry etching process (e.g., a half (etch back)) can be performed. 23 also reference surface, storage node contact (BC) exposed by number 2 (SP2) number of sub spacer 1308. volatile portion. The, sacrificial spacer (303a) can be etched sidewall. The upper surface of the upper surface of the bit line node contact (BC) number 2 sub-spacer (SP2) can be 151m. Etching the sacrificial spacer (303a) etching recipe (e.g., phosphoric acid) having etch selectivity with respect to using the wet etch process can be performed. The reference also 24, the upper surface of the storage node contact (BC), the upper surface of the spacer sub number 2 (SP2), spacer (SP1) sub number 1 exposed by the sacrificial spacer (303a) side wall portion and an upper side, sidewall spacer (SP1) sub number 1 portion and an upper side, and insulation pattern (240) [khen foam coverage is number 3 upper surface of spacer (307) can be formed. Spacer number 3 (307) is number 2 sub-spacer (SP2) can be identical to the material. For example, spacer number 3 (307) can be silicon nitride. The reference also 25, storage node contact (BC) of the top and insulation pattern (240a) spacer covering a top face of number 3 (307) number 3 (SP3) can be formed by sub-spacer as an etch mask. Etching, portions of the top and insulating pattern storage node contact (BC) (240) can be the upper portion of. Number 1 and number 2 (SP1, SP2) number 3 (SP3) includes a spacer sub sub spacers exposed by the sacrificial spacer (303a) side wall portion and an upper side, sacrificial spacer (303a) exposed by the upper surface of the sidewall of a portion (SP2) spacer (SP1) sub number 1 number 2 sub spacer covering a portion thereof can. 26 also reference surface, the top of the storage node contact (BC) as an etch mask can be disclosed. The, sidewall spacer (SP2) sub number 2 can be etched. The top surface of the storage node contact (BC) number 2 (SP2) low level than the upper surface of sub spacer can be located. Storage node contact (BC) (LP) can be disposed on landing pad. Landing pad (LP) (BC) are sequentially formed on the storage node electrode is barrier pattern (252) and metal pattern (254) can be comprising. Landing pads (LP) by spacer (SP1) portion of number 1 (O) space between sub, sacrificial spacer (303a) number 3 (SP3) to expose portions of the top of a portion sub spacer can be. 27 also reference surface, space (O) exposed by the sacrificial spacer (303a) can be a stand-alone selectively number. The, sub number 1 (SP1) (SP2) number 1 and number 2 (SP1) on spacer sub spacer between a void space between a spacer sub number 3 (SP3) on sub-spacer (AS) can be formed. In space (O) layer (276) can be formed. Layer (276) insulating the number 1 (276a) and number 2 insulating film (276b) can be comprising. Number 1 insulating film (276a) space (O) metal pattern is exposed by (254) side wall, space (O) exposed by the insulating pattern (240) side wall, number 1 and number 3 sub-spacers (SP1, SP3) (AS) of upper part of the space and surfaces thereof can covered comformally [khen foam. The, sub-spacer (SP1) number 1, number 2 (SP2) sub spacer, number 3 (SP3) sub spacer, number 2 and number 3 (SP2, SP3) (BC) sub spacers exposed by the storage node electrode is number 1 and a portion of the insulating film (246a) surrounded by a portion of the air gap (AG) can be formed. Number 2 insulating film (276b) insulating the number 1 (276a) can be formed on. The reference 3a also again, landing pad information on storage element (e.g., capacitor) (LP) can be formed. Or more, of the present invention in the embodiment described with reference to the attached drawing but, in the present invention is provided to the present invention is technical idea or person with skill in the art without changing its essential features can be understand other specific embodiment can form are disclosed. In the embodiment described above the exemplary non-limiting which is understood to all sides must substrate. 100: substrate BC: storage node contact BLS: bit line structures S1: number 1 spacer S2: number 2 spacer P1: number 1 portion P2: part number 2 P3: part number 3 SP1: number 1 sub spacer SP2: number 2 sub spacer SP3: number 3 sub spacer The present invention provides a semiconductor device with improved electrical properties. According to an embodiment of the present invention, the semiconductor device comprises: a substrate including an active area extended in a first direction; bit line structures crossing the active area in a second direction intersecting the first direction; a first spacer disposed on one side wall of the bit line structures on the substrate; and a storage node contact disposed on an end part of the active area between the adjacent bit line structures. The first spacer includes: a first part between each of the bit line structures and the storage node contact; a second part between the first part and the storage node contact; and a third part between the first part and the second part. The minimum vertical thickness of the first part is greater than the maximum vertical thickness of the third part, and the maximum vertical thickness of the third part can be greater than the maximum vertical thickness of the second part. COPYRIGHT KIPO 2017 Number 1 substrate including active region which extends in a direction; said active region overhangs transforming said number 1 number 2 bit line structures; said bit line structures on a substrate disposed on said one side wall each number 1 spacer; and adjacent said active region between said bit line structures comprising a storage node contact disposed on the end of, said number 1 spacer: said bit line structures with each said storage node contact between part number 1; said storage node contact portion between said number 1 number 2 portion; said number 1 and number 3 portion between the portion comprising said number 2, said number 1 portion of minimum vertical thickness greater than said number 3 maximum vertical thickness, maximum vertical thickness greater than the thickness of said number 3 of maximum vertical semiconductor device said number 2. According to Claim 1, including an air gap spacer insulating film and said number 1 with a center of said semiconductor device. According to Claim 1, insulating layer is used as said number 1 portion is number 1, number 2 insulating layer is used as said number 2 portion, and said number 3 portion is surrounded by a insulating film comprising said number 3 number 3 insulating air gap, said number 1 insulating film, said number 2 insulating film and said number 3 same material insulating layer including semiconductor device. According to Claim 1, minimum vertical thickness of said number 2 maximum vertical thickness of said number 3 same semiconductor device. According to Claim 1, said number 1 portion and said number 2 the top of the corner in which the exposed portion of the number 3 portion, said edge has an angled semiconductor device. According to Claim 1, said number 1 portion and said number 2 the top of the corner in which the exposed portion of the number 3 portion, a rounded edge said semiconductor device. According to Claim 1, disposed on a sidewall of said bit line structures each other, electrically connected to said storage node contact, said number 1 number 2 opposite spacer further comprising a spacer, said number 2 spacer: number 1 between said bit line structures with each storage node contact portion; said portion comprising said number 1 and number 2 between storage node contact portion, said number 1 portion of minimum vertical thickness greater than the thickness vertical semiconductor device maximum said number 2. According to Claim 7, said number 1 maximum vertical thickness of said number 1 minimum vertical thickness of said same semiconductor device. According to Claim 7, said number 2 maximum vertical thickness of said minimum vertical thickness of said number 2 same semiconductor device. According to Claim 1, said number 2 is formed on said semiconductor device positioned at a level higher than the upper surface of the drain.
